fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2025-12-22 15:40:11 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

aco: Assert that operands have the same byte offset when reassigning split vectors

Browse source 
This can not happen because the post-RA optimizer doesn't support sub dword
writes at the moment, but everytime I look at this I wonder if there might
be a bug here.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22821>
This commit is contained in:
Georg Lehmann 2023-05-03 11:24:19 +02:00 • committed by Marge Bot
parent d3f06cf5ce
commit c1cf40da8a
1 changed files with 5 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

5
src/amd/compiler/aco_optimizer_postRA.cpp
View file

@ -657,6 +657,11 @@ try_reassign_split_vector(pr_opt_ctx& ctx, aco_ptr<Instruction>& instr)
if (op.regClass() == s2 && reg.reg() % 2 != 0) if (op.regClass() == s2 && reg.reg() % 2 != 0)
break; break;
/* Sub dword operands might need updates to SDWA/opsel,
* but we only track full register writes at the moment.
*/
assert(op.physReg().byte() == reg.byte());
/* If there is only one use (left), recolor the split_vector definition */ /* If there is only one use (left), recolor the split_vector definition */
if (ctx.uses[op.tempId()] == 1) if (ctx.uses[op.tempId()] == 1)
def.setFixed(reg); def.setFixed(reg);