From c1af71c9c2740b7cc57eab8496b15efeaf53a6a4 Mon Sep 17 00:00:00 2001
From: Rohan Garg <rohan.garg@intel.com>
Date: Mon, 19 Aug 2024 12:00:19 +0200
Subject: [PATCH] anv,iris: prefix the argument format with XI for a upcoming
 refactor

Backport-to: 24.2
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30690>
---
 src/gallium/drivers/iris/iris_state.c | 2 +-
 src/intel/genxml/gen125.xml           | 2 +-
 src/intel/vulkan/genX_cmd_draw.c      | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c
index c498f50ab92..592a253c6d3 100644
--- a/src/gallium/drivers/iris/iris_state.c
+++ b/src/gallium/drivers/iris/iris_state.c
@@ -8634,7 +8634,7 @@ iris_upload_indirect_render_state(struct iris_context *ice,
 
    iris_emit_cmd(batch, GENX(EXECUTE_INDIRECT_DRAW), ind) {
       ind.ArgumentFormat             =
-         draw->index_size > 0 ? DRAWINDEXED : DRAW;
+         draw->index_size > 0 ? XI_DRAWINDEXED : XI_DRAW;
       ind.PredicateEnable            = use_predicate;
       ind.TBIMREnabled               = ice->state.use_tbimr;
       ind.MaxCount                   = indirect->draw_count;
diff --git a/src/intel/genxml/gen125.xml b/src/intel/genxml/gen125.xml
index adc069c6fcb..484ba17e1cc 100644
--- a/src/intel/genxml/gen125.xml
+++ b/src/intel/genxml/gen125.xml
@@ -1669,7 +1669,7 @@
     <field name="DWord Length" start="0" end="7" type="uint" default="4" />
     <field name="Predicate Enable" start="8" end="8" type="bool" />
     <field name="TBIMR Enabled" start="9" end="9" type="uint" />
-    <field name="Argument Format" start="10" end="11" type="uint">
+    <field name="Argument Format" start="10" end="11" type="uint" prefix="XI">
       <value name="DRAW" value="0" />
       <value name="DRAWINDEXED" value="1" />
       <value name="MESH_3D" value="2" />
diff --git a/src/intel/vulkan/genX_cmd_draw.c b/src/intel/vulkan/genX_cmd_draw.c
index 5f51a7f3583..07ff818eb91 100644
--- a/src/intel/vulkan/genX_cmd_draw.c
+++ b/src/intel/vulkan/genX_cmd_draw.c
@@ -1705,7 +1705,7 @@ emit_indirect_draws(struct anv_cmd_buffer *cmd_buffer,
 #if GFX_VERx10 >= 125
          genX(emit_breakpoint)(&cmd_buffer->batch, cmd_buffer->device, true);
          anv_batch_emit(&cmd_buffer->batch, GENX(EXECUTE_INDIRECT_DRAW), ind) {
-            ind.ArgumentFormat             = indexed ? DRAWINDEXED : DRAW;
+            ind.ArgumentFormat             = indexed ? XI_DRAWINDEXED : XI_DRAW;
             ind.TBIMREnabled               = cmd_buffer->state.gfx.dyn_state.use_tbimr;
             ind.PredicateEnable            =
                cmd_buffer->state.conditional_render_enabled;