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i965/eu: Fix a bunch of compression control bugs in the generator.

Browse source 
Most of these were resetting quarter control to zero incorrectly even
though everything they needed to do was disable instruction
compression -- The brw_SAMPLE() case was doing the right thing but it
can be simplified slightly by using the new compression control
interface.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
This commit is contained in:
Francisco Jerez 2016-05-18 15:29:27 -07:00
parent 3dffd81583
commit c19c3d3a52
2 changed files with 9 additions and 10 deletions
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17
src/mesa/drivers/dri/i965/brw_eu_emit.c
View file

@ -1744,10 +1744,10 @@ gen6_HALT(struct brw_codegen *p)
brw_set_src1(p, insn, brw_imm_d(0x0)); /* UIP and JIP, updated later. */
}
brw_inst_set_qtr_control(devinfo, insn, BRW_COMPRESSION_NONE);
if (p->compressed) {
brw_inst_set_exec_size(devinfo, insn, BRW_EXECUTE_16);
} else {
brw_inst_set_qtr_control(devinfo, insn, BRW_COMPRESSION_NONE);
brw_inst_set_exec_size(devinfo, insn, BRW_EXECUTE_8);
}
return insn;
@ -2110,10 +2110,11 @@ void brw_oword_block_write_scratch(struct brw_codegen *p,
struct brw_reg src_header = retype(brw_vec8_grf(0, 0),
BRW_REGISTER_TYPE_UW);
if (brw_inst_qtr_control(devinfo, insn) != BRW_COMPRESSION_NONE) {
brw_inst_set_qtr_control(devinfo, insn, BRW_COMPRESSION_NONE);
brw_inst_set_compression(devinfo, insn, false);
if (brw_inst_exec_size(devinfo, insn) >= 16)
src_header = vec16(src_header);
}
assert(brw_inst_pred_control(devinfo, insn) == BRW_PREDICATE_NONE);
if (devinfo->gen < 6)
brw_inst_set_base_mrf(devinfo, insn, mrf.nr);
@ -2224,7 +2225,7 @@ brw_oword_block_read_scratch(struct brw_codegen *p,
brw_inst *insn = next_insn(p, BRW_OPCODE_SEND);
assert(brw_inst_pred_control(devinfo, insn) == 0);
brw_inst_set_qtr_control(devinfo, insn, BRW_COMPRESSION_NONE);
brw_inst_set_compression(devinfo, insn, false);
brw_set_dest(p, insn, dest); /* UW? */
if (devinfo->gen >= 6) {
@ -2256,7 +2257,6 @@ gen7_block_read_scratch(struct brw_codegen *p,
brw_inst *insn = next_insn(p, BRW_OPCODE_SEND);
assert(brw_inst_pred_control(devinfo, insn) == BRW_PREDICATE_NONE);
brw_inst_set_qtr_control(devinfo, insn, BRW_COMPRESSION_NONE);
brw_set_dest(p, insn, retype(dest, BRW_REGISTER_TYPE_UW));
/* The HW requires that the header is present; this is to get the g0.5
@ -2370,7 +2370,7 @@ void brw_fb_WRITE(struct brw_codegen *p,
} else {
insn = next_insn(p, BRW_OPCODE_SEND);
}
brw_inst_set_qtr_control(devinfo, insn, BRW_COMPRESSION_NONE);
brw_inst_set_compression(devinfo, insn, false);
if (devinfo->gen >= 6) {
/* headerless version, just submit color payload */
@ -2440,8 +2440,7 @@ void brw_SAMPLE(struct brw_codegen *p,
* are allowed in SIMD16 mode and they could not work without SecHalf. For
* these reasons, we allow BRW_COMPRESSION_2NDHALF here.
*/
if (brw_inst_qtr_control(devinfo, insn) != BRW_COMPRESSION_2NDHALF)
brw_inst_set_qtr_control(devinfo, insn, BRW_COMPRESSION_NONE);
brw_inst_set_compression(devinfo, insn, false);
if (devinfo->gen < 6)
brw_inst_set_base_mrf(devinfo, insn, msg_reg_nr);

2
src/mesa/drivers/dri/i965/brw_fs_generator.cpp
View file

@ -1230,7 +1230,7 @@ fs_generator::generate_varying_pull_constant_load_gen4(fs_inst *inst,
gen6_resolve_implied_move(p, &header, inst->base_mrf);
brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
brw_inst_set_qtr_control(p->devinfo, send, BRW_COMPRESSION_NONE);
brw_inst_set_compression(devinfo, send, false);
brw_set_dest(p, send, retype(dst, BRW_REGISTER_TYPE_UW));
brw_set_src0(p, send, header);
if (devinfo->gen < 6)