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radeonsi: inline si_blend_color and si_clip_state structures

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better packing

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8653>
This commit is contained in:
Marek Olšák 2021-01-10 01:58:31 -05:00 • committed by Marge Bot
parent ca2062a394
commit c1957e58a6
3 changed files with 13 additions and 21 deletions
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4
src/gallium/drivers/radeonsi/si_gfx_cs.c
View file

@ -472,7 +472,7 @@ void si_begin_new_gfx_cs(struct si_context *ctx, bool first_cs)
/* These don't add any buffers, so skip them with shadowing. */
si_mark_atom_dirty(ctx, &ctx->atoms.s.clip_regs);
/* CLEAR_STATE sets zeros. */
if (!has_clear_state || ctx->clip_state.any_nonzeros)
if (!has_clear_state || ctx->clip_state_any_nonzeros)
si_mark_atom_dirty(ctx, &ctx->atoms.s.clip_state);
ctx->sample_locs_num_samples = 0;
si_mark_atom_dirty(ctx, &ctx->atoms.s.msaa_sample_locs);
@ -482,7 +482,7 @@ void si_begin_new_gfx_cs(struct si_context *ctx, bool first_cs)
si_mark_atom_dirty(ctx, &ctx->atoms.s.sample_mask);
si_mark_atom_dirty(ctx, &ctx->atoms.s.cb_render_state);
/* CLEAR_STATE sets zeros. */
if (!has_clear_state || ctx->blend_color.any_nonzeros)
if (!has_clear_state || ctx->blend_color_any_nonzeros)
si_mark_atom_dirty(ctx, &ctx->atoms.s.blend_color);
si_mark_atom_dirty(ctx, &ctx->atoms.s.db_render_state);
if (ctx->chip_class >= GFX9)

16
src/gallium/drivers/radeonsi/si_pipe.h
View file

@ -662,11 +662,6 @@ struct si_screen {
unsigned ge_wave_size;
};
struct si_blend_color {
struct pipe_blend_color state;
bool any_nonzeros;
};
struct si_sampler_view {
struct pipe_sampler_view base;
/* [0..7] = image descriptor
@ -762,11 +757,6 @@ struct si_viewports {
bool y_inverted;
};
struct si_clip_state {
struct pipe_clip_state state;
bool any_nonzeros;
};
struct si_streamout_target {
struct pipe_stream_output_target b;
@ -1029,10 +1019,12 @@ struct si_context {
unsigned sample_locs_num_samples;
uint16_t sample_mask;
unsigned last_cb_target_mask;
struct si_blend_color blend_color;
struct si_clip_state clip_state;
struct pipe_blend_color blend_color;
struct pipe_clip_state clip_state;
struct si_shader_data shader_pointers;
struct si_stencil_ref stencil_ref;
bool blend_color_any_nonzeros:1;
bool clip_state_any_nonzeros:1;
struct pipe_scissor_state scissors[SI_MAX_VIEWPORTS];
struct si_streamout streamout;
struct si_viewports viewports;

14
src/gallium/drivers/radeonsi/si_state.c
View file

@ -681,8 +681,8 @@ static void si_set_blend_color(struct pipe_context *ctx, const struct pipe_blend
struct si_context *sctx = (struct si_context *)ctx;
static const struct pipe_blend_color zeros;
sctx->blend_color.state = *state;
sctx->blend_color.any_nonzeros = memcmp(state, &zeros, sizeof(*state)) != 0;
sctx->blend_color = *state;
sctx->blend_color_any_nonzeros = memcmp(state, &zeros, sizeof(*state)) != 0;
si_mark_atom_dirty(sctx, &sctx->atoms.s.blend_color);
}
@ -692,7 +692,7 @@ static void si_emit_blend_color(struct si_context *sctx)
radeon_begin(cs);
radeon_set_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
radeon_emit_array(cs, (uint32_t *)sctx->blend_color.state.color, 4);
radeon_emit_array(cs, (uint32_t *)sctx->blend_color.color, 4);
radeon_end();
}
@ -706,11 +706,11 @@ static void si_set_clip_state(struct pipe_context *ctx, const struct pipe_clip_s
struct pipe_constant_buffer cb;
static const struct pipe_clip_state zeros;
if (memcmp(&sctx->clip_state.state, state, sizeof(*state)) == 0)
if (memcmp(&sctx->clip_state, state, sizeof(*state)) == 0)
return;
sctx->clip_state.state = *state;
sctx->clip_state.any_nonzeros = memcmp(state, &zeros, sizeof(*state)) != 0;
sctx->clip_state = *state;
sctx->clip_state_any_nonzeros = memcmp(state, &zeros, sizeof(*state)) != 0;
si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_state);
cb.buffer = NULL;
@ -726,7 +726,7 @@ static void si_emit_clip_state(struct si_context *sctx)
radeon_begin(cs);
radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP_0_X, 6 * 4);
radeon_emit_array(cs, (uint32_t *)sctx->clip_state.state.ucp, 6 * 4);
radeon_emit_array(cs, (uint32_t *)sctx->clip_state.ucp, 6 * 4);
radeon_end();
}