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ac/nir: add ac_nir_lower_ps
Lower ps output to nir_export_amd. Reviewed-by: Marek Olšák <marek.olsak@amd.com> Signed-off-by: Qiang Yu <yuq825@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21552>
This commit is contained in:
Qiang Yu
Marge Bot
parent
bf9c1699cd
commit
c182154456
3 changed files with 615 additions and 0 deletions
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@ -286,6 +286,30 @@ typedef struct {
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bool ac_nir_lower_subdword_loads(nir_shader *nir, ac_nir_lower_subdword_options options);
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typedef struct {
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enum radeon_family family;
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enum amd_gfx_level gfx_level;
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bool uses_discard;
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bool alpha_to_coverage_via_mrtz;
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bool dual_src_blend_swizzle;
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unsigned spi_shader_col_format;
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unsigned color_is_int8;
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unsigned color_is_int10;
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/* OpenGL only */
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bool clamp_color;
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bool alpha_to_one;
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enum pipe_compare_func alpha_func;
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unsigned broadcast_last_cbuf;
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/* Vulkan only */
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unsigned enable_mrt_output_nan_fixup;
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} ac_nir_lower_ps_options;
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void
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ac_nir_lower_ps(nir_shader *nir, const ac_nir_lower_ps_options *options);
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#ifdef __cplusplus
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}
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#endif
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590
src/amd/common/ac_nir_lower_ps.c
Normal file
590
src/amd/common/ac_nir_lower_ps.c
Normal file
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@ -0,0 +1,590 @@
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/*
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* Copyright 2023 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#include "ac_nir.h"
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#include "sid.h"
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#include "nir_builder.h"
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#include "nir_builtin_builder.h"
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typedef struct {
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const ac_nir_lower_ps_options *options;
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/* Add one for dual source blend second output. */
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nir_ssa_def *outputs[FRAG_RESULT_MAX + 1][4];
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nir_alu_type output_types[FRAG_RESULT_MAX + 1];
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/* MAX_DRAW_BUFFERS for MRT export, 1 for MRTZ export */
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nir_intrinsic_instr *exp[MAX_DRAW_BUFFERS + 1];
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unsigned exp_num;
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unsigned compacted_mrt_index;
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} lower_ps_state;
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#define DUAL_SRC_BLEND_SLOT FRAG_RESULT_MAX
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static bool
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gather_ps_store_output(nir_builder *b, nir_intrinsic_instr *intrin, lower_ps_state *s)
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{
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nir_io_semantics sem = nir_intrinsic_io_semantics(intrin);
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unsigned write_mask = nir_intrinsic_write_mask(intrin);
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unsigned component = nir_intrinsic_component(intrin);
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nir_alu_type type = nir_intrinsic_src_type(intrin);
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nir_ssa_def *store_val = intrin->src[0].ssa;
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b->cursor = nir_before_instr(&intrin->instr);
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unsigned slot = sem.dual_source_blend_index ?
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DUAL_SRC_BLEND_SLOT : sem.location;
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u_foreach_bit (i, write_mask) {
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unsigned comp = component + i;
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s->outputs[slot][comp] = nir_channel(b, store_val, i);
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}
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/* Same slot should have same type for all components. */
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assert(s->output_types[slot] == nir_type_invalid || s->output_types[slot] == type);
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s->output_types[slot] = type;
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nir_instr_remove(&intrin->instr);
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return true;
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}
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static bool
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lower_ps_intrinsic(nir_builder *b, nir_instr *instr, void *state)
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{
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lower_ps_state *s = (lower_ps_state *)state;
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if (instr->type != nir_instr_type_intrinsic)
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return false;
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nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
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if (intrin->intrinsic == nir_intrinsic_store_output)
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return gather_ps_store_output(b, intrin, s);
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return false;
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}
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static void
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emit_ps_color_clamp_and_alpha_test(nir_builder *b, lower_ps_state *s)
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{
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uint32_t color_mask =
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BITFIELD_BIT(FRAG_RESULT_COLOR) |
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BITFIELD_RANGE(FRAG_RESULT_DATA0, MAX_DRAW_BUFFERS);
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uint32_t color_outputs =
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(b->shader->info.outputs_written & color_mask) |
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/* both dual source blend outputs use FRAG_RESULT_DATA0 slot in nir,
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* but we use an extra slot number in lower_ps_state for the second
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* output
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*/
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BITFIELD_BIT(DUAL_SRC_BLEND_SLOT);
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u_foreach_bit (slot, color_outputs) {
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if (s->options->clamp_color) {
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for (int i = 0; i < 4; i++) {
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if (s->outputs[slot][i])
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s->outputs[slot][i] = nir_fsat(b, s->outputs[slot][i]);
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}
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}
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if (s->options->alpha_to_one) {
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/* any one has written to this slot */
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if (s->output_types[slot] != nir_type_invalid) {
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unsigned bit_size = nir_alu_type_get_type_size(s->output_types[slot]);
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s->outputs[slot][3] = nir_imm_floatN_t(b, 1, bit_size);
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}
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}
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if (slot == FRAG_RESULT_COLOR || slot == FRAG_RESULT_DATA0) {
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if (s->options->alpha_func == PIPE_FUNC_ALWAYS) {
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/* always pass, do nothing */
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} else if (s->options->alpha_func == PIPE_FUNC_NEVER) {
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nir_discard(b);
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} else if (s->outputs[slot][3]) {
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nir_ssa_def *ref = nir_load_alpha_reference_amd(b);
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nir_ssa_def *cond =
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nir_compare_func(b, s->options->alpha_func, s->outputs[slot][3], ref);
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nir_discard_if(b, nir_inot(b, cond));
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}
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}
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}
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}
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static void
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emit_ps_mrtz_export(nir_builder *b, lower_ps_state *s)
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{
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nir_ssa_def *mrtz_alpha = NULL;
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if (s->options->alpha_to_coverage_via_mrtz) {
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mrtz_alpha = s->outputs[FRAG_RESULT_COLOR][3] ?
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s->outputs[FRAG_RESULT_COLOR][3] :
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s->outputs[FRAG_RESULT_DATA0][3];
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}
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nir_ssa_def *depth = s->outputs[FRAG_RESULT_DEPTH][0];
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nir_ssa_def *stencil = s->outputs[FRAG_RESULT_STENCIL][0];
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nir_ssa_def *sample_mask = s->outputs[FRAG_RESULT_SAMPLE_MASK][0];
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/* skip mrtz export if no one has written to any of them */
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if (!depth && !stencil && !sample_mask && !mrtz_alpha)
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return;
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uint64_t outputs_written = b->shader->info.outputs_written;
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/* use outputs_written to determine export format as we use it to set
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* R_028710_SPI_SHADER_Z_FORMAT instead of relying on the real store ouput,
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* because store ouput may be optimized out.
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*/
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unsigned format =
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ac_get_spi_shader_z_format(outputs_written & BITFIELD64_BIT(FRAG_RESULT_DEPTH),
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outputs_written & BITFIELD64_BIT(FRAG_RESULT_STENCIL),
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outputs_written & BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK),
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s->options->alpha_to_coverage_via_mrtz);
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nir_ssa_def *undef = nir_ssa_undef(b, 1, 32);
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nir_ssa_def *outputs[4] = {undef, undef, undef, undef};
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unsigned write_mask = 0;
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unsigned flags = 0;
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if (format == V_028710_SPI_SHADER_UINT16_ABGR) {
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assert(!depth && !mrtz_alpha);
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if (s->options->gfx_level < GFX11)
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flags |= AC_EXP_FLAG_COMPRESSED;
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if (stencil) {
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outputs[0] = nir_ishl_imm(b, stencil, 16);
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write_mask |= s->options->gfx_level >= GFX11 ? 0x1 : 0x3;
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}
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if (sample_mask) {
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outputs[1] = sample_mask;
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write_mask |= s->options->gfx_level >= GFX11 ? 0x2 : 0xc;
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}
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} else {
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if (depth) {
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outputs[0] = depth;
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write_mask |= 0x1;
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}
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if (stencil) {
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outputs[1] = stencil;
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write_mask |= 0x2;
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}
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if (sample_mask) {
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outputs[2] = sample_mask;
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write_mask |= 0x4;
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}
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if (mrtz_alpha) {
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outputs[3] = mrtz_alpha;
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write_mask |= 0x8;
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}
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}
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/* GFX6 (except OLAND and HAINAN) has a bug that it only looks at the
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* X writemask component.
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*/
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if (s->options->gfx_level == GFX6 &&
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s->options->family != CHIP_OLAND &&
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s->options->family != CHIP_HAINAN) {
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write_mask |= 0x1;
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}
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s->exp[s->exp_num++] = nir_export_amd(b, nir_vec(b, outputs, 4),
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.base = V_008DFC_SQ_EXP_MRTZ,
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.write_mask = write_mask,
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.flags = flags);
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}
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static unsigned
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get_ps_color_export_target(lower_ps_state *s)
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{
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unsigned target = V_008DFC_SQ_EXP_MRT + s->compacted_mrt_index;
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if (s->options->dual_src_blend_swizzle && s->compacted_mrt_index < 2)
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target += 21;
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s->compacted_mrt_index++;
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return target;
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}
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static bool
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emit_ps_color_export(nir_builder *b, lower_ps_state *s, gl_frag_result slot, unsigned cbuf)
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{
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assert(cbuf < 8);
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unsigned spi_shader_col_format = (s->options->spi_shader_col_format >> (cbuf * 4)) & 0xf;
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if (spi_shader_col_format == V_028714_SPI_SHADER_ZERO)
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return false;
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/* get target after checking spi_shader_col_format as we need to increase
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* compacted_mrt_index anyway regardless of whether the export is built
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*/
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unsigned target = get_ps_color_export_target(s);
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nir_alu_type type = s->output_types[slot];
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/* no one has written to this slot */
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if (type == nir_type_invalid)
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return false;
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bool is_int8 = s->options->color_is_int8 & BITFIELD_BIT(cbuf);
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bool is_int10 = s->options->color_is_int10 & BITFIELD_BIT(cbuf);
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bool enable_mrt_output_nan_fixup =
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s->options->enable_mrt_output_nan_fixup & BITFIELD_BIT(cbuf);
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nir_ssa_def *undef = nir_ssa_undef(b, 1, 32);
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nir_ssa_def *outputs[4] = {undef, undef, undef, undef};
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unsigned write_mask = 0;
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unsigned flags = 0;
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nir_alu_type base_type = nir_alu_type_get_base_type(type);
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unsigned type_size = nir_alu_type_get_type_size(type);
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nir_ssa_def *data[4];
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memcpy(data, s->outputs[slot], sizeof(data));
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/* Replace NaN by zero (for 32-bit float formats) to fix game bugs if requested. */
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if (enable_mrt_output_nan_fixup && type == nir_type_float32) {
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for (int i = 0; i < 4; i++) {
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if (data[i]) {
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nir_ssa_def *isnan = nir_fisnan(b, data[i]);
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data[i] = nir_bcsel(b, isnan, nir_imm_float(b, 0), data[i]);
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}
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}
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}
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switch (spi_shader_col_format) {
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case V_028714_SPI_SHADER_32_R:
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if (!data[0])
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return false;
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outputs[0] = nir_convert_to_bit_size(b, data[0], base_type, 32);
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write_mask = 0x1;
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break;
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case V_028714_SPI_SHADER_32_GR:
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if (!data[0] && !data[1])
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return false;
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if (data[0]) {
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outputs[0] = nir_convert_to_bit_size(b, data[0], base_type, 32);
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write_mask |= 0x1;
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}
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if (data[1]) {
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outputs[1] = nir_convert_to_bit_size(b, data[1], base_type, 32);
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write_mask |= 0x2;
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}
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break;
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case V_028714_SPI_SHADER_32_AR:
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if (!data[0] && !data[3])
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return false;
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if (data[0]) {
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outputs[0] = nir_convert_to_bit_size(b, data[0], base_type, 32);
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write_mask |= 0x1;
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}
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if (data[3]) {
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unsigned index = s->options->gfx_level >= GFX10 ? 1 : 3;
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outputs[index] = nir_convert_to_bit_size(b, data[3], base_type, 32);
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write_mask |= BITFIELD_BIT(index);
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}
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break;
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case V_028714_SPI_SHADER_32_ABGR:
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for (int i = 0; i < 4; i++) {
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if (data[i]) {
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outputs[i] = nir_convert_to_bit_size(b, data[i], base_type, 32);
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write_mask |= BITFIELD_BIT(i);
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}
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}
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break;
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default: {
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nir_op pack_op = nir_op_pack_32_2x16;
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bool need_clamp = false;
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switch (spi_shader_col_format) {
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case V_028714_SPI_SHADER_FP16_ABGR:
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if (type_size == 32)
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pack_op = nir_op_pack_half_2x16;
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break;
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case V_028714_SPI_SHADER_UINT16_ABGR:
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if (type_size == 32) {
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pack_op = nir_op_pack_uint_2x16;
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need_clamp = is_int8 || is_int10;
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}
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break;
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case V_028714_SPI_SHADER_SINT16_ABGR:
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if (type_size == 32) {
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pack_op = nir_op_pack_sint_2x16;
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need_clamp = is_int8 || is_int10;
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}
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break;
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case V_028714_SPI_SHADER_UNORM16_ABGR:
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pack_op = nir_op_pack_unorm_2x16;
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break;
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case V_028714_SPI_SHADER_SNORM16_ABGR:
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pack_op = nir_op_pack_snorm_2x16;
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break;
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default:
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unreachable("unsupport color export format");
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break;
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}
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/* clamp 32bit output for 8/10 bit color component */
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for (int i = 0; i < 4; i++) {
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if (need_clamp && data[i]) {
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int max_value = is_int10 ? (i == 3 ? 3 : 1023) : 255;
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data[i] = nir_umin(b, data[i], nir_imm_int(b, max_value));
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}
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}
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for (int i = 0; i < 2; i++) {
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nir_ssa_def *lo = data[i * 2];
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nir_ssa_def *hi = data[i * 2 + 1];
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if (!lo && !hi)
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continue;
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lo = lo ? lo : nir_ssa_undef(b, 1, type_size);
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hi = hi ? hi : nir_ssa_undef(b, 1, type_size);
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nir_ssa_def *vec = nir_vec2(b, lo, hi);
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outputs[i] = nir_build_alu1(b, pack_op, vec);
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if (s->options->gfx_level >= GFX11)
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write_mask |= BITFIELD_BIT(i);
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else
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write_mask |= 0x3 << (i * 2);
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}
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if (s->options->gfx_level < GFX11)
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flags |= AC_EXP_FLAG_COMPRESSED;
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}
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}
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s->exp[s->exp_num++] = nir_export_amd(b, nir_vec(b, outputs, 4),
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.base = target,
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.write_mask = write_mask,
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.flags = flags);
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return true;
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}
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static void
|
||||
emit_ps_dual_src_blend_swizzle(nir_builder *b, lower_ps_state *s, unsigned first_color_export)
|
||||
{
|
||||
assert(s->exp_num > first_color_export + 1);
|
||||
|
||||
nir_intrinsic_instr *mrt0_exp = s->exp[first_color_export];
|
||||
nir_intrinsic_instr *mrt1_exp = s->exp[first_color_export + 1];
|
||||
|
||||
/* There are some instructions which operate mrt1_exp's argument
|
||||
* between mrt0_exp and mrt1_exp. Move mrt0_exp next to mrt1_exp,
|
||||
* so that we can swizzle their arguments.
|
||||
*/
|
||||
unsigned target0 = nir_intrinsic_base(mrt0_exp);
|
||||
unsigned target1 = nir_intrinsic_base(mrt1_exp);
|
||||
if (target0 > target1) {
|
||||
/* mrt0 export is after mrt1 export, this happens when src0 is missing,
|
||||
* so we emit mrt1 first then emit an empty mrt0.
|
||||
*
|
||||
* swap the pointer
|
||||
*/
|
||||
nir_intrinsic_instr *tmp = mrt0_exp;
|
||||
mrt0_exp = mrt1_exp;
|
||||
mrt1_exp = tmp;
|
||||
|
||||
/* move mrt1_exp down to after mrt0_exp */
|
||||
nir_instr_move(nir_after_instr(&mrt0_exp->instr), &mrt1_exp->instr);
|
||||
} else {
|
||||
/* move mrt0_exp down to before mrt1_exp */
|
||||
nir_instr_move(nir_before_instr(&mrt1_exp->instr), &mrt0_exp->instr);
|
||||
}
|
||||
|
||||
uint32_t mrt0_write_mask = nir_intrinsic_write_mask(mrt0_exp);
|
||||
uint32_t mrt1_write_mask = nir_intrinsic_write_mask(mrt1_exp);
|
||||
uint32_t write_mask = mrt0_write_mask | mrt1_write_mask;
|
||||
|
||||
nir_ssa_def *mrt0_arg = mrt0_exp->src[0].ssa;
|
||||
nir_ssa_def *mrt1_arg = mrt1_exp->src[0].ssa;
|
||||
|
||||
/* Swizzle code is right before mrt0_exp. */
|
||||
b->cursor = nir_before_instr(&mrt0_exp->instr);
|
||||
|
||||
nir_ssa_def *undef = nir_ssa_undef(b, 1, 32);
|
||||
nir_ssa_def *arg0_vec[4] = {undef, undef, undef, undef};
|
||||
nir_ssa_def *arg1_vec[4] = {undef, undef, undef, undef};
|
||||
|
||||
/* For illustration, originally
|
||||
* lane0 export arg00 and arg01
|
||||
* lane1 export arg10 and arg11.
|
||||
*
|
||||
* After the following operation
|
||||
* lane0 export arg00 and arg10
|
||||
* lane1 export arg01 and arg11.
|
||||
*/
|
||||
u_foreach_bit (i, write_mask) {
|
||||
nir_ssa_def *arg0 = nir_channel(b, mrt0_arg, i);
|
||||
nir_ssa_def *arg1 = nir_channel(b, mrt1_arg, i);
|
||||
|
||||
/* swap odd,even lanes of arg0 */
|
||||
arg0 = nir_quad_swizzle_amd(b, arg0, .swizzle_mask = 0b10110001);
|
||||
|
||||
/* swap even lanes between arg0 and arg1 */
|
||||
nir_ssa_def *tid = nir_load_subgroup_invocation(b);
|
||||
nir_ssa_def *is_even = nir_ieq_imm(b, nir_iand_imm(b, tid, 1), 0);
|
||||
|
||||
nir_ssa_def *tmp = arg0;
|
||||
arg0 = nir_bcsel(b, is_even, arg1, arg0);
|
||||
arg1 = nir_bcsel(b, is_even, tmp, arg1);
|
||||
|
||||
/* swap odd,even lanes again for arg0 */
|
||||
arg0 = nir_quad_swizzle_amd(b, arg0, .swizzle_mask = 0b10110001);
|
||||
|
||||
arg0_vec[i] = arg0;
|
||||
arg1_vec[i] = arg1;
|
||||
}
|
||||
|
||||
nir_instr_rewrite_src_ssa(&mrt0_exp->instr, &mrt0_exp->src[0], nir_vec(b, arg0_vec, 4));
|
||||
nir_instr_rewrite_src_ssa(&mrt1_exp->instr, &mrt1_exp->src[0], nir_vec(b, arg1_vec, 4));
|
||||
|
||||
nir_intrinsic_set_write_mask(mrt0_exp, write_mask);
|
||||
nir_intrinsic_set_write_mask(mrt1_exp, write_mask);
|
||||
}
|
||||
|
||||
static void
|
||||
emit_ps_null_export(nir_builder *b, lower_ps_state *s)
|
||||
{
|
||||
/* Gfx10+ doesn't need to export anything if we don't need to export the EXEC mask
|
||||
* for discard.
|
||||
*/
|
||||
if (s->options->gfx_level >= GFX10 && !s->options->uses_discard)
|
||||
return;
|
||||
|
||||
/* Gfx11 doesn't support null exports, and mrt0 should be exported instead. */
|
||||
unsigned target = s->options->gfx_level >= GFX11 ?
|
||||
V_008DFC_SQ_EXP_MRT : V_008DFC_SQ_EXP_NULL;
|
||||
|
||||
nir_export_amd(b, nir_ssa_undef(b, 4, 32),
|
||||
.base = target,
|
||||
.flags = AC_EXP_FLAG_VALID_MASK | AC_EXP_FLAG_DONE);
|
||||
}
|
||||
|
||||
static void
|
||||
export_ps_outputs(nir_shader *nir, lower_ps_state *s)
|
||||
{
|
||||
nir_function_impl *impl = nir_shader_get_entrypoint(nir);
|
||||
|
||||
nir_builder builder;
|
||||
nir_builder *b = &builder;
|
||||
nir_builder_init(b, impl);
|
||||
|
||||
b->cursor = nir_after_cf_list(&impl->body);
|
||||
|
||||
emit_ps_color_clamp_and_alpha_test(b, s);
|
||||
|
||||
emit_ps_mrtz_export(b, s);
|
||||
|
||||
unsigned first_color_export = s->exp_num;
|
||||
|
||||
/* When dual src blend is enabled and we need both src0 and src1
|
||||
* export present, try to export both src, and add an empty export
|
||||
* for either src missing.
|
||||
*/
|
||||
if (s->output_types[DUAL_SRC_BLEND_SLOT] != nir_type_invalid ||
|
||||
s->options->dual_src_blend_swizzle) {
|
||||
unsigned slot;
|
||||
if (s->output_types[FRAG_RESULT_COLOR] != nir_type_invalid) {
|
||||
/* when dual source blending, there must be only one color buffer */
|
||||
assert(s->options->broadcast_last_cbuf == 0);
|
||||
slot = FRAG_RESULT_COLOR;
|
||||
} else {
|
||||
slot = FRAG_RESULT_DATA0;
|
||||
}
|
||||
|
||||
bool src0_exported = emit_ps_color_export(b, s, slot, 0);
|
||||
/* src1 use cubf1 info, when dual src blend is enabled it's
|
||||
* same as cbuf0, but when dual src blend is disabled it's used
|
||||
* to disable src1 export.
|
||||
*/
|
||||
bool src1_exported = emit_ps_color_export(b, s, DUAL_SRC_BLEND_SLOT, 1);
|
||||
|
||||
bool need_empty_export =
|
||||
/* miss src1, need to add src1 only when swizzle case */
|
||||
(src0_exported && !src1_exported && s->options->dual_src_blend_swizzle) ||
|
||||
/* miss src0, always need to add src0 */
|
||||
(!src0_exported && src1_exported);
|
||||
|
||||
if (need_empty_export) {
|
||||
/* set to expected value */
|
||||
s->compacted_mrt_index = src0_exported ? 1 : 0;
|
||||
|
||||
unsigned target = get_ps_color_export_target(s);
|
||||
|
||||
s->exp[s->exp_num++] =
|
||||
nir_export_amd(b, nir_ssa_undef(b, 4, 32), .base = target);
|
||||
}
|
||||
} else {
|
||||
if (s->output_types[FRAG_RESULT_COLOR] != nir_type_invalid) {
|
||||
/* write to all color buffers */
|
||||
for (int cbuf = 0; cbuf <= s->options->broadcast_last_cbuf; cbuf++)
|
||||
emit_ps_color_export(b, s, FRAG_RESULT_COLOR, cbuf);
|
||||
} else {
|
||||
for (int cbuf = 0; cbuf < MAX_DRAW_BUFFERS; cbuf++) {
|
||||
unsigned slot = FRAG_RESULT_DATA0 + cbuf;
|
||||
emit_ps_color_export(b, s, slot, cbuf);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (s->exp_num) {
|
||||
if (s->options->dual_src_blend_swizzle)
|
||||
emit_ps_dual_src_blend_swizzle(b, s, first_color_export);
|
||||
|
||||
/* Specify that this is the last export */
|
||||
nir_intrinsic_instr *final_exp = s->exp[s->exp_num - 1];
|
||||
unsigned final_exp_flags = nir_intrinsic_flags(final_exp);
|
||||
final_exp_flags |= AC_EXP_FLAG_DONE | AC_EXP_FLAG_VALID_MASK;
|
||||
nir_intrinsic_set_flags(final_exp, final_exp_flags);
|
||||
} else {
|
||||
emit_ps_null_export(b, s);
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
ac_nir_lower_ps(nir_shader *nir, const ac_nir_lower_ps_options *options)
|
||||
{
|
||||
lower_ps_state state = {
|
||||
.options = options,
|
||||
};
|
||||
|
||||
nir_shader_instructions_pass(nir, lower_ps_intrinsic,
|
||||
nir_metadata_block_index | nir_metadata_dominance,
|
||||
&state);
|
||||
|
||||
export_ps_outputs(nir, &state);
|
||||
}
|
||||
|
|
@ -98,6 +98,7 @@ amd_common_files = files(
|
|||
'ac_nir_lower_taskmesh_io_to_mem.c',
|
||||
'ac_nir_lower_tess_io_to_mem.c',
|
||||
'ac_nir_lower_ngg.c',
|
||||
'ac_nir_lower_ps.c',
|
||||
'amd_family.c',
|
||||
'ac_perfcounter.c',
|
||||
'ac_perfcounter.h',
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue