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nak: Rename OpBrev to OpBRev
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26550>
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parent
9b68c77abb
commit
c14f4cc052
4 changed files with 12 additions and 12 deletions
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@ -643,7 +643,7 @@ impl SM70Instr {
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self.set_pred_src(87..90, 90, op.accum);
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}
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fn encode_brev(&mut self, op: &OpBrev) {
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fn encode_brev(&mut self, op: &OpBRev) {
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self.encode_alu(
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0x101,
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Some(op.dst),
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@ -1995,7 +1995,7 @@ impl SM70Instr {
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Op::DMul(op) => si.encode_dmul(&op),
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Op::DSetP(op) => si.encode_dsetp(&op),
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Op::MuFu(op) => si.encode_mufu(&op),
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Op::Brev(op) => si.encode_brev(&op),
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Op::BRev(op) => si.encode_brev(&op),
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Op::Flo(op) => si.encode_flo(&op),
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Op::IAbs(op) => si.encode_iabs(&op),
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Op::IAdd3(op) => si.encode_iadd3(&op),
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@ -535,7 +535,7 @@ impl<'a> ShaderFromNir<'a> {
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}
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nir_op_bitfield_reverse => {
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let dst = b.alloc_ssa(RegFile::GPR, 1);
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b.push_op(OpBrev {
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b.push_op(OpBRev {
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dst: dst.into(),
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src: srcs[0],
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});
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@ -605,7 +605,7 @@ impl<'a> ShaderFromNir<'a> {
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}
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nir_op_find_lsb => {
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let tmp = b.alloc_ssa(RegFile::GPR, 1);
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b.push_op(OpBrev {
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b.push_op(OpBRev {
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dst: tmp.into(),
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src: srcs[0],
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});
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@ -2580,19 +2580,19 @@ impl_display_for_op!(OpDSetP);
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#[repr(C)]
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#[derive(SrcsAsSlice, DstsAsSlice)]
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pub struct OpBrev {
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pub struct OpBRev {
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pub dst: Dst,
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#[src_type(ALU)]
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pub src: Src,
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}
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impl DisplayOp for OpBrev {
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impl DisplayOp for OpBRev {
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fn fmt_op(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
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write!(f, "brev {}", self.src,)
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write!(f, "brev {}", self.src)
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}
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}
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impl_display_for_op!(OpBrev);
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impl_display_for_op!(OpBRev);
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#[repr(C)]
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#[derive(SrcsAsSlice, DstsAsSlice)]
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@ -4727,7 +4727,7 @@ pub enum Op {
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DMnMx(OpDMnMx),
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DMul(OpDMul),
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DSetP(OpDSetP),
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Brev(OpBrev),
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BRev(OpBRev),
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Flo(OpFlo),
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IAbs(OpIAbs),
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INeg(OpINeg),
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@ -5171,7 +5171,7 @@ impl Instr {
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| Op::DSetP(_) => false,
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// Integer ALU
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Op::Brev(_) | Op::Flo(_) | Op::PopC(_) => false,
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Op::BRev(_) | Op::Flo(_) | Op::PopC(_) => false,
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Op::IAbs(_)
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| Op::INeg(_)
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| Op::IAdd2(_)
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@ -316,7 +316,7 @@ fn legalize_sm50_instr(
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Op::PopC(op) => {
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copy_alu_src_if_not_reg(b, &mut op.src, SrcType::ALU);
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}
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Op::Brev(op) => {
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Op::BRev(op) => {
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copy_alu_src_if_not_reg(b, &mut op.src, SrcType::ALU);
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}
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Op::FMnMx(op) => {
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@ -432,7 +432,7 @@ fn legalize_sm70_instr(
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}
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copy_alu_src_if_not_reg(b, src0, SrcType::F64);
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}
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Op::Brev(_) | Op::Flo(_) | Op::IAbs(_) | Op::INeg(_) => (),
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Op::BRev(_) | Op::Flo(_) | Op::IAbs(_) | Op::INeg(_) => (),
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Op::IAdd3(op) => {
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let [ref mut src0, ref mut src1, ref mut src2] = op.srcs;
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swap_srcs_if_not_reg(src0, src1);
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