From c097c3745582a8fc5aaf7530665ab56244e55fe3 Mon Sep 17 00:00:00 2001 From: Pierre-Eric Pelloux-Prayer Date: Fri, 18 Oct 2024 14:33:07 +0200 Subject: [PATCH] ac: add 'polaris12' gpu to ac_fake_hw_db MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reviewed-by: Marek Olšák Reviewed-by: Samuel Pitoiset Part-of: --- src/amd/common/ac_fake_hw_db.h | 26 +++++++++++++++++++ src/amd/common/ac_surface_meta_address_test.c | 6 ++++- 2 files changed, 31 insertions(+), 1 deletion(-) diff --git a/src/amd/common/ac_fake_hw_db.h b/src/amd/common/ac_fake_hw_db.h index b09b6adfcee..a33af3dbce1 100644 --- a/src/amd/common/ac_fake_hw_db.h +++ b/src/amd/common/ac_fake_hw_db.h @@ -23,6 +23,31 @@ typedef void (*gpu_init_func)(struct radeon_info *info); +static void init_polaris12(struct radeon_info *info) +{ + info->family = CHIP_POLARIS12; + info->gfx_level = GFX8; + info->family_id = AMDGPU_FAMILY_VI; + info->chip_external_rev = 0x64; + info->use_display_dcc_unaligned = false; + info->use_display_dcc_with_retile_blit = false; + info->has_graphics = true; + info->tcc_cache_line_size = 64; + info->max_render_backends = 4; + + uint32_t si_tile_mode_array[] = { + 0x00800150, 0x00800950, 0x00801150, 0x00801950, 0x00802950, + 0x00802948, 0x00802954, 0x00802954, 0x00000144, 0x02000148, + 0x02000150, 0x06000154, 0x06000154, 0x02400148, 0x02400150, + 0x02400170, 0x06400154, 0x06400154, 0x0040014c, 0x0100014c, + 0x0100015c, 0x01000174, 0x01000164, 0x01000164, 0x0040015c, + 0x01000160, 0x01000178, 0x02c00148, 0x02c00150, 0x06c00154, + 0x06c00154, 0x00000000 + }; + memcpy(info->si_tile_mode_array, si_tile_mode_array, sizeof(si_tile_mode_array)); + info->gb_addr_config = 0x22011002; +} + static void init_vega10(struct radeon_info *info) { info->family = CHIP_VEGA10; @@ -168,6 +193,7 @@ struct ac_fake_hw { }; static struct ac_fake_hw ac_fake_hw_db[] = { + {"polaris12", init_polaris12}, {"vega10", init_vega10, 4, 2, 2, 2}, {"vega10_diff_bank", init_vega10, 3, 2, 2, 2}, {"vega10_diff_rb", init_vega10, 4, 2, 2, 0}, diff --git a/src/amd/common/ac_surface_meta_address_test.c b/src/amd/common/ac_surface_meta_address_test.c index 0c0c022f17a..d07c44d66fa 100644 --- a/src/amd/common/ac_surface_meta_address_test.c +++ b/src/amd/common/ac_surface_meta_address_test.c @@ -660,6 +660,10 @@ static void run_cmask_address_test(const char *name, const struct radeon_info *i if (info->gfx_level >= GFX11) return; + /* The test doesn't support GFX8- */ + if (info->gfx_level < GFX9) + return; + /* The test coverage is reduced for Gitlab CI because it timeouts. */ if (!full) { first_size = last_size = 0; @@ -712,7 +716,7 @@ int main(int argc, char **argv) struct radeon_info info = { .drm_major = 0 }; get_radeon_info(&info, &ac_fake_hw_db[i]); - if (info.gfx_level >= GFX12) + if (info.gfx_level < GFX9 || info.gfx_level >= GFX12) continue; run_dcc_address_test(ac_fake_hw_db[i].name, &info, full);