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ir3/postsched: Don't use SSA source information

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This was only used for calculating if a source is a tex or SFU
instruction, which is easily replacable. It's going away with the new
RA.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9842>
This commit is contained in:
Connor Abbott 2021-03-23 18:13:26 +01:00 • committed by Emma Anholt
parent c947475533
commit c0789395e0
1 changed files with 24 additions and 4 deletions
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28
src/freedreno/ir3/ir3_postsched.c
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@ -70,6 +70,8 @@ struct ir3_postsched_node {
struct ir3_instruction *instr;
bool partially_evaluated_path;
bool has_tex_src, has_sfu_src;
unsigned delay;
unsigned max_delay;
};
@ -77,6 +79,20 @@ struct ir3_postsched_node {
#define foreach_sched_node(__n, __list) \
list_for_each_entry(struct ir3_postsched_node, __n, __list, dag.link)
static bool
has_tex_src(struct ir3_instruction *instr)
{
struct ir3_postsched_node *node = instr->data;
return node->has_tex_src;
}
static bool
has_sfu_src(struct ir3_instruction *instr)
{
struct ir3_postsched_node *node = instr->data;
return node->has_sfu_src;
}
static void
schedule(struct ir3_postsched_ctx *ctx, struct ir3_instruction *instr)
{
@ -98,7 +114,7 @@ schedule(struct ir3_postsched_ctx *ctx, struct ir3_instruction *instr)
if (is_sfu(instr)) {
ctx->sfu_delay = 8;
} else if (check_src_cond(instr, is_sfu)) {
} else if (has_sfu_src(instr)) {
ctx->sfu_delay = 0;
} else if (ctx->sfu_delay > 0) {
ctx->sfu_delay--;
@ -106,7 +122,7 @@ schedule(struct ir3_postsched_ctx *ctx, struct ir3_instruction *instr)
if (is_tex_or_prefetch(instr)) {
ctx->tex_delay = 10;
} else if (check_src_cond(instr, is_tex_or_prefetch)) {
} else if (has_tex_src(instr)) {
ctx->tex_delay = 0;
} else if (ctx->tex_delay > 0) {
ctx->tex_delay--;
@ -140,12 +156,12 @@ static bool
would_sync(struct ir3_postsched_ctx *ctx, struct ir3_instruction *instr)
{
if (ctx->sfu_delay) {
if (check_src_cond(instr, is_sfu))
if (has_sfu_src(instr))
return true;
}
if (ctx->tex_delay) {
if (check_src_cond(instr, is_tex_or_prefetch))
if (has_tex_src(instr))
return true;
}
@ -374,6 +390,10 @@ add_single_reg_dep(struct ir3_postsched_deps_state *state,
if (src_n >= 0 && dep && state->direction == F) {
unsigned d = ir3_delayslots(dep->instr, node->instr, src_n, true);
node->delay = MAX2(node->delay, d);
if (is_tex_or_prefetch(dep->instr))
node->has_tex_src = true;
if (is_tex_or_prefetch(dep->instr))
node->has_sfu_src = true;
}
add_dep(state, dep, node);