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radeon/vcn: Use the correct pitch for chroma surface.

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The pitch of the chroma plane isn't necessarily half that of the
luma plane, as tiling (and presumably even linear) swizzle modes
apply some alignment.

Fixes: 35e25ea1d0 ("ac/surface: allow non-DCC modifiers for YUV on GFX9+")
Reviewed-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10638>
This commit is contained in:
Bas Nieuwenhuizen 2021-05-04 23:34:42 +00:00 • committed by Marge Bot
parent d8ab0ec8e4
commit c05e48308b
1 changed files with 2 additions and 2 deletions
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4
src/gallium/drivers/radeon/radeon_vcn_dec.c
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@ -1649,7 +1649,7 @@ static struct pb_buffer *rvcn_dec_message_decode(struct radeon_decoder *dec,
decode->db_surf_tile_config = 0;
decode->dt_pitch = luma->surface.u.gfx9.surf_pitch * luma->surface.blk_w;
decode->dt_uv_pitch = decode->dt_pitch / 2;
decode->dt_uv_pitch = chroma->surface.u.gfx9.surf_pitch * chroma->surface.blk_w;
if (luma->surface.meta_offset) {
RVID_ERR("DCC surfaces not supported.\n");
@ -1675,7 +1675,7 @@ static struct pb_buffer *rvcn_dec_message_decode(struct radeon_decoder *dec,
decode->dt_chroma_bottom_offset = decode->dt_chroma_top_offset;
}
if (dec->stream_type == RDECODE_CODEC_AV1)
decode->db_pitch_uv = decode->db_pitch / 2;
decode->db_pitch_uv = chroma->surface.u.gfx9.surf_pitch * chroma->surface.blk_w;
if (encrypted) {
assert(sscreen->info.has_tmz_support);