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radv: disable unsupported hw shader stages for RGP on GFX11+

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Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25171>
This commit is contained in:
Samuel Pitoiset 2023-09-12 08:49:33 +02:00 • committed by Marge Bot
parent 4f5dd54713
commit c04b10155e
3 changed files with 21 additions and 6 deletions
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13
src/amd/common/ac_sqtt.c
View file

@ -277,3 +277,16 @@ ac_sqtt_get_trace(struct ac_sqtt *data, const struct radeon_info *info,
return true;
}
uint32_t
ac_sqtt_get_shader_mask(const struct radeon_info *info)
{
unsigned shader_mask = 0x7f; /* all shader stages */
if (info->gfx_level >= GFX11) {
/* Disable unsupported hw shader stages */
shader_mask &= ~(0x02 /* VS */ | 0x08 /* ES */ | 0x20 /* LS */);
}
return shader_mask;
}

2
src/amd/common/ac_sqtt.h
View file

@ -554,4 +554,6 @@ bool ac_sqtt_se_is_disabled(const struct radeon_info *info, unsigned se);
bool ac_sqtt_get_trace(struct ac_sqtt *sqtt, const struct radeon_info *info,
struct ac_sqtt_trace *sqtt_trace);
uint32_t ac_sqtt_get_shader_mask(const struct radeon_info *info);
#endif

12
src/amd/vulkan/radv_sqtt.c
View file

@ -78,6 +78,7 @@ radv_emit_sqtt_start(const struct radv_device *device, struct radeon_cmdbuf *cs,
const enum amd_gfx_level gfx_level = device->physical_device->rad_info.gfx_level;
uint32_t shifted_size = device->sqtt.buffer_size >> SQTT_BUFFER_ALIGN_SHIFT;
const struct radeon_info *rad_info = &device->physical_device->rad_info;
const unsigned shader_mask = ac_sqtt_get_shader_mask(rad_info);
unsigned max_se = rad_info->max_se;
for (unsigned se = 0; se < max_se; se++) {
@ -101,8 +102,8 @@ radv_emit_sqtt_start(const struct radv_device *device, struct radeon_cmdbuf *cs,
radeon_set_perfctr_reg(gfx_level, qf, cs, R_0367A0_SQ_THREAD_TRACE_BUF0_BASE, shifted_va);
radeon_set_perfctr_reg(gfx_level, qf, cs, R_0367B4_SQ_THREAD_TRACE_MASK,
S_0367B4_WTYPE_INCLUDE(0x7f) | /* all shader stages */
S_0367B4_SA_SEL(0) | S_0367B4_WGP_SEL(first_active_cu / 2) | S_0367B4_SIMD_SEL(0));
S_0367B4_WTYPE_INCLUDE(shader_mask) | S_0367B4_SA_SEL(0) |
S_0367B4_WGP_SEL(first_active_cu / 2) | S_0367B4_SIMD_SEL(0));
uint32_t sqtt_token_mask = S_0367B8_REG_INCLUDE(V_0367B8_REG_INCLUDE_SQDEC | V_0367B8_REG_INCLUDE_SHDEC |
V_0367B8_REG_INCLUDE_GFXUDEC | V_0367B8_REG_INCLUDE_COMP |
@ -132,9 +133,8 @@ radv_emit_sqtt_start(const struct radv_device *device, struct radeon_cmdbuf *cs,
radeon_set_privileged_config_reg(cs, R_008D00_SQ_THREAD_TRACE_BUF0_BASE, shifted_va);
radeon_set_privileged_config_reg(cs, R_008D14_SQ_THREAD_TRACE_MASK,
S_008D14_WTYPE_INCLUDE(0x7f) | /* all shader stages */
S_008D14_SA_SEL(0) | S_008D14_WGP_SEL(first_active_cu / 2) |
S_008D14_SIMD_SEL(0));
S_008D14_WTYPE_INCLUDE(shader_mask) | S_008D14_SA_SEL(0) |
S_008D14_WGP_SEL(first_active_cu / 2) | S_008D14_SIMD_SEL(0));
uint32_t sqtt_token_mask = S_008D18_REG_INCLUDE(V_008D18_REG_INCLUDE_SQDEC | V_008D18_REG_INCLUDE_SHDEC |
V_008D18_REG_INCLUDE_GFXUDEC | V_008D18_REG_INCLUDE_COMP |
@ -681,7 +681,7 @@ radv_begin_sqtt(struct radv_queue *queue)
if (device->spm.bo) {
/* Enable all shader stages by default. */
radv_perfcounter_emit_shaders(cs, 0x7f);
radv_perfcounter_emit_shaders(cs, ac_sqtt_get_shader_mask(&device->physical_device->rad_info));
radv_emit_spm_setup(device, cs);
}