brw: Add assembler support for DPAS

Allow us to parse instructions in a form we currently generate

```
dpas.8x8(8)     g55<1>F         g47<1,1,0>F     g31<1,1,0>HF    g39<1,1,0>HF { align1 WE_all 1Q $4 };
```

Regions are not really needed, but this will be handled in a later patch
(that will also stop printing the regions).

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34031>

src/intel/compiler/brw_eu.h

@@ -1425,6 +1425,19 @@ brw_pixel_interp_desc(UNUSED const struct intel_device_info *devinfo,
            SET_BITS(simd_mode, 16, 16));
 }
 
+static inline enum gfx12_systolic_depth
+translate_systolic_depth(unsigned d)
+{
+   /* Could also return (ffs(d) - 1) & 3. */
+   switch (d) {
+   case 2:  return BRW_SYSTOLIC_DEPTH_2;
+   case 4:  return BRW_SYSTOLIC_DEPTH_4;
+   case 8:  return BRW_SYSTOLIC_DEPTH_8;
+   case 16: return BRW_SYSTOLIC_DEPTH_16;
+   default: unreachable("Invalid systolic depth.");
+   }
+}
+
 /**
  * Send message to shared unit \p sfid with a possibly indirect descriptor \p
  * desc.  If \p desc is not an immediate it will be transparently loaded to an

src/intel/compiler/brw_generator.cpp

@@ -740,19 +740,6 @@ brw_generator::enable_debug(const char *shader_name)
    this->shader_name = shader_name;
 }
 
-static gfx12_systolic_depth
-translate_systolic_depth(unsigned d)
-{
-   /* Could also return (ffs(d) - 1) & 3. */
-   switch (d) {
-   case 2:  return BRW_SYSTOLIC_DEPTH_2;
-   case 4:  return BRW_SYSTOLIC_DEPTH_4;
-   case 8:  return BRW_SYSTOLIC_DEPTH_8;
-   case 16: return BRW_SYSTOLIC_DEPTH_16;
-   default: unreachable("Invalid systolic depth.");
-   }
-}
-
 int
 brw_generator::generate_code(const cfg_t *cfg, int dispatch_width,
                             struct brw_shader_stats shader_stats,

src/intel/compiler/brw_gram.y

@@ -333,6 +333,7 @@ i965_asm_set_instruction_options(struct brw_codegen *p,
    struct instoption instoption;
    struct msgdesc msgdesc;
    struct tgl_swsb depinfo;
+   struct { int sdepth; int rcount; } dpas_params;
    brw_eu_inst *instruction;
 }
 
@@ -367,7 +368,7 @@ i965_asm_set_instruction_options(struct brw_codegen *p,
 %token <integer> ADD ADD3 ADDC AND ASR AVG
 %token <integer> BFE BFI1 BFI2 BFB BFREV BRC BRD BREAK
 %token <integer> CALL CALLA CASE CBIT CMP CMPN CONT CSEL
-%token <integer> DIM DO DPAS DPASW DP2 DP3 DP4 DP4A DPH
+%token <integer> DIM DO DPAS DP2 DP3 DP4 DP4A DPH
 %token <integer> ELSE ENDIF FBH FBL FORK FRC
 %token <integer> GOTO
 %token <integer> HALT
@@ -542,6 +543,9 @@ i965_asm_set_instruction_options(struct brw_codegen *p,
 
 %type <depinfo> depinfo
 
+/* DPAS */
+%token <dpas_params> DPAS_PARAMS
+
 %code {
 
 static void
@@ -862,6 +866,26 @@ ternaryinstruction:
       brw_eu_inst_set_exec_size(p->devinfo, brw_last_inst, $5);
       brw_eu_inst_set_group(p->devinfo, brw_last_inst, $10.chan_offset);
    }
+   |
+   predicate DPAS DPAS_PARAMS saturate cond_mod execsize dst src src src instoptions
+   {
+      assert(p->devinfo->verx10 >= 125);
+
+      brw_set_default_access_mode(p, $11.access_mode);
+
+      brw_DPAS(p, translate_systolic_depth($3.sdepth), $3.rcount, $7, $8, $9, $10);
+      brw_pop_insn_state(p);
+      i965_asm_set_instruction_options(p, $11);
+      if ($5.cond_modifier) {
+         brw_eu_inst_set_cond_modifier(p->devinfo,
+                                       brw_last_inst,
+                                       $5.cond_modifier);
+      }
+
+      brw_eu_inst_set_saturate(p->devinfo, brw_last_inst, $4);
+      brw_eu_inst_set_exec_size(p->devinfo, brw_last_inst, $6);
+      brw_eu_inst_set_group(p->devinfo, brw_last_inst, $11.chan_offset);
+   }
    ;
 
 ternaryopcodes:

src/intel/compiler/brw_lex.l

@@ -76,6 +76,7 @@ dp2             { yylval.integer = BRW_OPCODE_DP2; return DP2; }
 dp3             { yylval.integer = BRW_OPCODE_DP3; return DP3; }
 dp4             { yylval.integer = BRW_OPCODE_DP4; return DP4; }
 dp4a            { yylval.integer = BRW_OPCODE_DP4A; return DP4A; }
+dpas            { yylval.integer = BRW_OPCODE_DPAS; return DPAS; }
 dph             { yylval.integer = BRW_OPCODE_DPH; return DPH; }
 else            { yylval.integer = BRW_OPCODE_ELSE; return ELSE; }
 endif           { yylval.integer = BRW_OPCODE_ENDIF; return ENDIF; }
@@ -419,6 +420,13 @@ sr[0-9]+        { yylval.integer = atoi(yytext + 2); return STATEREG; }
 "$"[0-9]*".src" { yylval.integer = atoi(yytext + 1); return SBID_WAIT_SRC; }
 "$"[0-9]*".dst" { yylval.integer = atoi(yytext + 1); return SBID_WAIT_DST; }
 
+ /* DPAS params. */
+"."[1-9][0-9]*x[1-9][0-9]* {
+        yylval.dpas_params.sdepth = atoi(yytext + 1);
+        yylval.dpas_params.rcount = atoi(strchr(yytext, 'x') + 1);
+        return DPAS_PARAMS;
+}
+
 \n      { yycolumn = 1; }
 
 .       {