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https://gitlab.freedesktop.org/mesa/mesa.git
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intel/compiler: Use C helpers to access builtin types
Remove usage of C++ static members as they are going to be removed. Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26658>
This commit is contained in:
Caio Oliveira
Marge Bot
parent
90e364edb0
commit
bfc953add7
19 changed files with 578 additions and 578 deletions
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@ -185,7 +185,7 @@ fs_visitor::VARYING_PULL_CONSTANT_LOAD(const fs_builder &bld,
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* later notice that those loads are all the same and eliminate the
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* redundant ones.
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*/
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fs_reg vec4_offset = vgrf(glsl_type::uint_type);
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fs_reg vec4_offset = vgrf(glsl_uint_type());
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bld.ADD(vec4_offset, varying_offset, brw_imm_ud(const_offset & ~0xf));
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/* The pull load message will load a vec4 (16 bytes). If we are loading
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@ -6855,11 +6855,11 @@ fs_visitor::run_gs()
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payload_ = new gs_thread_payload(*this);
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this->final_gs_vertex_count = vgrf(glsl_type::uint_type);
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this->final_gs_vertex_count = vgrf(glsl_uint_type());
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if (gs_compile->control_data_header_size_bits > 0) {
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/* Create a VGRF to store accumulated control data bits. */
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this->control_data_bits = vgrf(glsl_type::uint_type);
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this->control_data_bits = vgrf(glsl_uint_type());
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/* If we're outputting more than 32 control data bits, then EmitVertex()
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* will set control_data_bits to 0 after emitting the first vertex.
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@ -538,7 +538,7 @@ optimize_frontfacing_ternary(nir_to_brw_state &ntb,
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/* nir_opt_algebraic should have gotten rid of bcsel(b, a, a) */
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assert(value1 == -value2);
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fs_reg tmp = s.vgrf(glsl_type::int_type);
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fs_reg tmp = s.vgrf(glsl_int_type());
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if (devinfo->ver >= 12) {
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/* Bit 15 of g1.1 is 0 if the polygon is front facing. */
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@ -859,7 +859,7 @@ emit_fsign(nir_to_brw_state &ntb, const fs_builder &bld, const nir_alu_instr *in
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* - We need to produce a DF result.
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*/
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fs_reg zero = s.vgrf(glsl_type::double_type);
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fs_reg zero = s.vgrf(glsl_double_type());
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bld.MOV(zero, setup_imm_df(bld, 0.0));
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bld.CMP(bld.null_reg_df(), op[0], zero, BRW_CONDITIONAL_NZ);
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@ -1571,7 +1571,7 @@ fs_nir_emit_alu(nir_to_brw_state &ntb, nir_alu_instr *instr,
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case nir_op_fceil: {
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op[0].negate = !op[0].negate;
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fs_reg temp = s.vgrf(glsl_type::float_type);
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fs_reg temp = s.vgrf(glsl_float_type());
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bld.RNDD(temp, op[0]);
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temp.negate = true;
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inst = bld.MOV(result, temp);
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@ -1932,7 +1932,7 @@ fs_nir_emit_alu(nir_to_brw_state &ntb, nir_alu_instr *instr,
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if (devinfo->ver <= 5 &&
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!result.is_null() &&
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(instr->instr.pass_flags & BRW_NIR_BOOLEAN_MASK) == BRW_NIR_BOOLEAN_NEEDS_RESOLVE) {
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fs_reg masked = s.vgrf(glsl_type::int_type);
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fs_reg masked = s.vgrf(glsl_int_type());
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bld.AND(masked, result, brw_imm_d(1));
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masked.negate = true;
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bld.MOV(retype(result, BRW_REGISTER_TYPE_D), masked);
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@ -2250,10 +2250,10 @@ fs_visitor::emit_gs_control_data_bits(const fs_reg &vertex_count)
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fs_reg channel_mask, per_slot_offset;
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if (gs_compile->control_data_header_size_bits > 32)
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channel_mask = vgrf(glsl_type::uint_type);
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channel_mask = vgrf(glsl_uint_type());
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if (gs_compile->control_data_header_size_bits > 128)
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per_slot_offset = vgrf(glsl_type::uint_type);
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per_slot_offset = vgrf(glsl_uint_type());
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/* Figure out which DWord we're trying to write to using the formula:
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*
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@ -3314,7 +3314,7 @@ emit_mcs_fetch(nir_to_brw_state &ntb, const fs_reg &coordinate, unsigned compone
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{
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const fs_builder &bld = ntb.bld;
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const fs_reg dest = ntb.s.vgrf(glsl_type::uvec4_type);
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const fs_reg dest = ntb.s.vgrf(glsl_uvec4_type());
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fs_reg srcs[TEX_LOGICAL_NUM_SRCS];
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srcs[TEX_LOGICAL_SRC_COORDINATE] = coordinate;
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@ -3803,8 +3803,8 @@ emit_samplemaskin_setup(nir_to_brw_state &ntb)
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if (ntb.system_values[SYSTEM_VALUE_SAMPLE_ID].file == BAD_FILE)
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ntb.system_values[SYSTEM_VALUE_SAMPLE_ID] = emit_sampleid_setup(ntb);
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fs_reg one = s.vgrf(glsl_type::int_type);
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fs_reg enabled_mask = s.vgrf(glsl_type::int_type);
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fs_reg one = s.vgrf(glsl_int_type());
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fs_reg enabled_mask = s.vgrf(glsl_int_type());
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abld.MOV(one, brw_imm_d(1));
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abld.SHL(enabled_mask, one, ntb.system_values[SYSTEM_VALUE_SAMPLE_ID]);
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fs_reg mask = bld.vgrf(BRW_REGISTER_TYPE_D);
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@ -4241,7 +4241,7 @@ fs_nir_emit_fs_intrinsic(nir_to_brw_state &ntb,
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dest.type = BRW_REGISTER_TYPE_F;
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if (devinfo->ver < 6 && interp_mode == INTERP_MODE_SMOOTH) {
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fs_reg tmp = s.vgrf(glsl_type::float_type);
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fs_reg tmp = s.vgrf(glsl_float_type());
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bld.emit(FS_OPCODE_LINTERP, tmp, dst_xy, interp);
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bld.MUL(offset(dest, bld, i), tmp, s.pixel_w);
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} else {
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@ -7673,7 +7673,7 @@ fs_nir_emit_surface_atomic(nir_to_brw_state &ntb, const fs_builder &bld,
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brw_imm_ud(nir_intrinsic_base(instr) +
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nir_src_as_uint(instr->src[0]));
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} else {
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srcs[SURFACE_LOGICAL_SRC_ADDRESS] = s.vgrf(glsl_type::uint_type);
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srcs[SURFACE_LOGICAL_SRC_ADDRESS] = s.vgrf(glsl_uint_type());
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bld.ADD(srcs[SURFACE_LOGICAL_SRC_ADDRESS],
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retype(get_nir_src(ntb, instr->src[0]), BRW_REGISTER_TYPE_UD),
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brw_imm_ud(nir_intrinsic_base(instr)));
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@ -7881,7 +7881,7 @@ fs_nir_emit_texture(nir_to_brw_state &ntb,
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if (instr->texture_index == 0 && is_resource_src(nir_src))
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srcs[TEX_LOGICAL_SRC_SURFACE] = get_resource_nir_src(ntb, nir_src);
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if (srcs[TEX_LOGICAL_SRC_SURFACE].file == BAD_FILE) {
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fs_reg tmp = s.vgrf(glsl_type::uint_type);
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fs_reg tmp = s.vgrf(glsl_uint_type());
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bld.ADD(tmp, src, brw_imm_ud(instr->texture_index));
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srcs[TEX_LOGICAL_SRC_SURFACE] = bld.emit_uniformize(tmp);
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}
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@ -7894,7 +7894,7 @@ fs_nir_emit_texture(nir_to_brw_state &ntb,
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if (instr->sampler_index == 0 && is_resource_src(nir_src))
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srcs[TEX_LOGICAL_SRC_SAMPLER] = get_resource_nir_src(ntb, nir_src);
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if (srcs[TEX_LOGICAL_SRC_SAMPLER].file == BAD_FILE) {
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fs_reg tmp = s.vgrf(glsl_type::uint_type);
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fs_reg tmp = s.vgrf(glsl_uint_type());
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bld.ADD(tmp, src, brw_imm_ud(instr->sampler_index));
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srcs[TEX_LOGICAL_SRC_SAMPLER] = bld.emit_uniformize(tmp);
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}
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@ -8014,7 +8014,7 @@ fs_nir_emit_texture(nir_to_brw_state &ntb,
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if (srcs[TEX_LOGICAL_SRC_MCS].file == BRW_IMMEDIATE_VALUE) {
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bld.MOV(dst, brw_imm_ud(0u));
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} else if (devinfo->ver >= 9) {
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fs_reg tmp = s.vgrf(glsl_type::uint_type);
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fs_reg tmp = s.vgrf(glsl_uint_type());
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bld.OR(tmp, srcs[TEX_LOGICAL_SRC_MCS],
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offset(srcs[TEX_LOGICAL_SRC_MCS], bld, 1));
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bld.CMP(dst, tmp, brw_imm_ud(0u), BRW_CONDITIONAL_EQ);
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@ -8106,7 +8106,7 @@ fs_nir_emit_texture(nir_to_brw_state &ntb,
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dest_size >= 3 && devinfo->ver < 7) {
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/* Gfx4-6 return 0 instead of 1 for single layer surfaces. */
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fs_reg depth = offset(dst, bld, 2);
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nir_dest[2] = s.vgrf(glsl_type::int_type);
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nir_dest[2] = s.vgrf(glsl_int_type());
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bld.emit_minmax(nir_dest[2], depth, brw_imm_d(1), BRW_CONDITIONAL_GE);
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}
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@ -96,8 +96,8 @@ fs_visitor::emit_interpolation_setup_gfx4()
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struct brw_reg g1_uw = retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW);
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fs_builder abld = fs_builder(this).at_end().annotate("compute pixel centers");
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this->pixel_x = vgrf(glsl_type::uint_type);
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this->pixel_y = vgrf(glsl_type::uint_type);
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this->pixel_x = vgrf(glsl_uint_type());
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this->pixel_y = vgrf(glsl_uint_type());
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this->pixel_x.type = BRW_REGISTER_TYPE_UW;
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this->pixel_y.type = BRW_REGISTER_TYPE_UW;
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abld.ADD(this->pixel_x,
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@ -111,7 +111,7 @@ fs_visitor::emit_interpolation_setup_gfx4()
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abld = bld.annotate("compute pixel deltas from v0");
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this->delta_xy[BRW_BARYCENTRIC_PERSPECTIVE_PIXEL] =
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vgrf(glsl_type::vec2_type);
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vgrf(glsl_vec2_type());
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const fs_reg &delta_xy = this->delta_xy[BRW_BARYCENTRIC_PERSPECTIVE_PIXEL];
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const fs_reg xstart(negate(brw_vec1_grf(1, 0)));
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const fs_reg ystart(negate(brw_vec1_grf(1, 1)));
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@ -141,11 +141,11 @@ fs_visitor::emit_interpolation_setup_gfx4()
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/* Compute wpos.w. It's always in our setup, since it's needed to
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* interpolate the other attributes.
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*/
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this->wpos_w = vgrf(glsl_type::float_type);
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this->wpos_w = vgrf(glsl_float_type());
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abld.emit(FS_OPCODE_LINTERP, wpos_w, delta_xy,
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component(interp_reg(VARYING_SLOT_POS, 3), 0));
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/* Compute the pixel 1/W value from wpos.w. */
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this->pixel_w = vgrf(glsl_type::float_type);
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this->pixel_w = vgrf(glsl_float_type());
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abld.emit(SHADER_OPCODE_RCP, this->pixel_w, wpos_w);
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}
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@ -156,8 +156,8 @@ fs_visitor::emit_interpolation_setup_gfx6()
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const fs_builder bld = fs_builder(this).at_end();
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fs_builder abld = bld.annotate("compute pixel centers");
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this->pixel_x = vgrf(glsl_type::float_type);
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this->pixel_y = vgrf(glsl_type::float_type);
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this->pixel_x = vgrf(glsl_float_type());
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this->pixel_y = vgrf(glsl_float_type());
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const struct brw_wm_prog_key *wm_key = (brw_wm_prog_key*) this->key;
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struct brw_wm_prog_data *wm_prog_data = brw_wm_prog_data(prog_data);
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@ -481,7 +481,7 @@ fs_visitor::emit_interpolation_setup_gfx6()
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if (wm_prog_data->uses_src_w) {
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abld = bld.annotate("compute pos.w");
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this->pixel_w = fetch_payload_reg(abld, fs_payload().source_w_reg);
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this->wpos_w = vgrf(glsl_type::float_type);
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this->wpos_w = vgrf(glsl_float_type());
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abld.emit(SHADER_OPCODE_RCP, this->wpos_w, this->pixel_w);
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}
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@ -839,7 +839,7 @@ fs_visitor::emit_urb_writes(const fs_reg &gs_vertex_count)
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per_slot_offsets = brw_imm_ud(output_vertex_size_owords *
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gs_vertex_count.ud);
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} else {
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per_slot_offsets = vgrf(glsl_type::uint_type);
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per_slot_offsets = vgrf(glsl_uint_type());
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bld.MUL(per_slot_offsets, gs_vertex_count,
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brw_imm_ud(output_vertex_size_owords));
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}
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@ -1672,7 +1672,7 @@ vec4_visitor::get_timestamp()
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BRW_SWIZZLE_XYZW,
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WRITEMASK_XYZW));
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dst_reg dst = dst_reg(this, glsl_type::uvec4_type);
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dst_reg dst = dst_reg(this, glsl_uvec4_type());
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vec4_instruction *mov = emit(MOV(dst, ts));
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/* We want to read the 3 fields we care about (mostly field 0, but also 2)
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@ -2233,7 +2233,7 @@ vec4_visitor::lower_64bit_mad_to_mul_add()
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if (type_sz(inst->dst.type) != 8)
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continue;
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dst_reg mul_dst = dst_reg(this, glsl_type::dvec4_type);
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dst_reg mul_dst = dst_reg(this, glsl_dvec4_type());
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/* Use the copy constructor so we copy all relevant instruction fields
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* from the original mad into the add and mul instructions
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@ -169,7 +169,7 @@ opt_cmod_propagation_local(bblock_t *block, vec4_visitor *v)
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(inst->src[0].swizzle == BRW_SWIZZLE_WWWW &&
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scan_inst->dst.writemask == WRITEMASK_W))) {
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if (inst->dst.writemask != scan_inst->dst.writemask) {
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src_reg temp(v, glsl_type::vec4_type, 1);
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src_reg temp(v, glsl_vec4_type(), 1);
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/* Given a sequence like:
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*
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@ -171,7 +171,7 @@ vec4_gs_visitor::emit_prolog()
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inst->force_writemask_all = true;
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/* Create a virtual register to hold the vertex count */
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this->vertex_count = src_reg(this, glsl_type::uint_type);
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this->vertex_count = src_reg(this, glsl_uint_type());
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/* Initialize the vertex_count register to 0 */
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this->current_annotation = "initialize vertex_count";
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@ -182,7 +182,7 @@ vec4_gs_visitor::emit_prolog()
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/* Create a virtual register to hold the current set of control data
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* bits.
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*/
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this->control_data_bits = src_reg(this, glsl_type::uint_type);
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this->control_data_bits = src_reg(this, glsl_uint_type());
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/* If we're outputting more than 32 control data bits, then EmitVertex()
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* will set control_data_bits to 0 after emitting the first vertex.
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@ -316,9 +316,9 @@ vec4_gs_visitor::emit_control_data_bits()
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*
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* dword_index = (vertex_count - 1) >> (6 - log2(bits_per_vertex))
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*/
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src_reg dword_index(this, glsl_type::uint_type);
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src_reg dword_index(this, glsl_uint_type());
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if (urb_write_flags) {
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src_reg prev_count(this, glsl_type::uint_type);
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src_reg prev_count(this, glsl_uint_type());
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emit(ADD(dst_reg(prev_count), this->vertex_count,
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brw_imm_ud(0xffffffffu)));
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unsigned log2_bits_per_vertex =
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@ -340,7 +340,7 @@ vec4_gs_visitor::emit_control_data_bits()
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/* Set the per-slot offset to dword_index / 4, to that we'll write to
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* the appropriate OWORD within the control data header.
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*/
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src_reg per_slot_offset(this, glsl_type::uint_type);
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src_reg per_slot_offset(this, glsl_uint_type());
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emit(SHR(dst_reg(per_slot_offset), dword_index, brw_imm_ud(2u)));
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emit(GS_OPCODE_SET_WRITE_OFFSET, mrf_reg, per_slot_offset,
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brw_imm_ud(1u));
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@ -354,13 +354,13 @@ vec4_gs_visitor::emit_control_data_bits()
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* GS_OPCODE_PREPARE_CHANNEL_MASKS tries to OR the two masks
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* together.
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*/
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src_reg channel(this, glsl_type::uint_type);
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src_reg channel(this, glsl_uint_type());
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inst = emit(AND(dst_reg(channel), dword_index, brw_imm_ud(3u)));
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inst->force_writemask_all = true;
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src_reg one(this, glsl_type::uint_type);
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src_reg one(this, glsl_uint_type());
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inst = emit(MOV(dst_reg(one), brw_imm_ud(1u)));
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inst->force_writemask_all = true;
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src_reg channel_mask(this, glsl_type::uint_type);
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src_reg channel_mask(this, glsl_uint_type());
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inst = emit(SHL(dst_reg(channel_mask), one, channel));
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inst->force_writemask_all = true;
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emit(GS_OPCODE_PREPARE_CHANNEL_MASKS, dst_reg(channel_mask),
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@ -400,11 +400,11 @@ vec4_gs_visitor::set_stream_control_data_bits(unsigned stream_id)
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return;
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/* reg::sid = stream_id */
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src_reg sid(this, glsl_type::uint_type);
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src_reg sid(this, glsl_uint_type());
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emit(MOV(dst_reg(sid), brw_imm_ud(stream_id)));
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/* reg:shift_count = 2 * (vertex_count - 1) */
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src_reg shift_count(this, glsl_type::uint_type);
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src_reg shift_count(this, glsl_uint_type());
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emit(SHL(dst_reg(shift_count), this->vertex_count, brw_imm_ud(1u)));
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|
||||
/* Note: we're relying on the fact that the GEN SHL instruction only pays
|
||||
|
|
@ -412,7 +412,7 @@ vec4_gs_visitor::set_stream_control_data_bits(unsigned stream_id)
|
|||
* architecture, stream_id << 2 * (vertex_count - 1) is equivalent to
|
||||
* stream_id << ((2 * (vertex_count - 1)) % 32).
|
||||
*/
|
||||
src_reg mask(this, glsl_type::uint_type);
|
||||
src_reg mask(this, glsl_uint_type());
|
||||
emit(SHL(dst_reg(mask), sid, shift_count));
|
||||
emit(OR(dst_reg(this->control_data_bits), this->control_data_bits, mask));
|
||||
}
|
||||
|
|
@ -548,11 +548,11 @@ vec4_gs_visitor::gs_end_primitive()
|
|||
*/
|
||||
|
||||
/* control_data_bits |= 1 << ((vertex_count - 1) % 32) */
|
||||
src_reg one(this, glsl_type::uint_type);
|
||||
src_reg one(this, glsl_uint_type());
|
||||
emit(MOV(dst_reg(one), brw_imm_ud(1u)));
|
||||
src_reg prev_count(this, glsl_type::uint_type);
|
||||
src_reg prev_count(this, glsl_uint_type());
|
||||
emit(ADD(dst_reg(prev_count), this->vertex_count, brw_imm_ud(0xffffffffu)));
|
||||
src_reg mask(this, glsl_type::uint_type);
|
||||
src_reg mask(this, glsl_uint_type());
|
||||
/* Note: we're relying on the fact that the GEN SHL instruction only pays
|
||||
* attention to the lower 5 bits of its second source argument, so on this
|
||||
* architecture, 1 << (vertex_count - 1) is equivalent to 1 <<
|
||||
|
|
|
|||
|
|
@ -430,7 +430,7 @@ vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
|
|||
dest = get_nir_def(instr->def);
|
||||
|
||||
src = src_reg(ATTR, nir_intrinsic_base(instr) + load_offset,
|
||||
glsl_type::uvec4_type);
|
||||
glsl_uvec4_type());
|
||||
src = retype(src, dest.type);
|
||||
|
||||
/* Swizzle source based on component layout qualifier */
|
||||
|
|
@ -469,7 +469,7 @@ vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
|
|||
src_reg lod = brw_imm_d(0);
|
||||
int param_base = inst->base_mrf;
|
||||
int writemask = WRITEMASK_X;
|
||||
emit(MOV(dst_reg(MRF, param_base, glsl_type::int_type, writemask), lod));
|
||||
emit(MOV(dst_reg(MRF, param_base, glsl_int_type(), writemask), lod));
|
||||
|
||||
emit(inst);
|
||||
break;
|
||||
|
|
@ -645,7 +645,7 @@ vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
|
|||
* per-channel and add the base UBO index; we have to select a value
|
||||
* from any live channel.
|
||||
*/
|
||||
surf_index = src_reg(this, glsl_type::uint_type);
|
||||
surf_index = src_reg(this, glsl_uint_type());
|
||||
emit(MOV(dst_reg(surf_index), get_nir_src(instr->src[0], nir_type_int32,
|
||||
instr->num_components)));
|
||||
surf_index = emit_uniformize(surf_index);
|
||||
|
|
@ -677,7 +677,7 @@ vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
|
|||
}
|
||||
}
|
||||
} else {
|
||||
offset_reg = src_reg(this, glsl_type::uint_type);
|
||||
offset_reg = src_reg(this, glsl_uint_type());
|
||||
emit(MOV(dst_reg(offset_reg),
|
||||
get_nir_src(instr->src[1], nir_type_uint32, 1)));
|
||||
}
|
||||
|
|
@ -686,14 +686,14 @@ vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
|
|||
if (push_reg.file != BAD_FILE) {
|
||||
packed_consts = push_reg;
|
||||
} else if (instr->def.bit_size == 32) {
|
||||
packed_consts = src_reg(this, glsl_type::vec4_type);
|
||||
packed_consts = src_reg(this, glsl_vec4_type());
|
||||
emit_pull_constant_load_reg(dst_reg(packed_consts),
|
||||
surf_index,
|
||||
offset_reg,
|
||||
NULL, NULL /* before_block/inst */);
|
||||
prog_data->base.has_ubo_pull = true;
|
||||
} else {
|
||||
src_reg temp = src_reg(this, glsl_type::dvec4_type);
|
||||
src_reg temp = src_reg(this, glsl_dvec4_type());
|
||||
src_reg temp_float = retype(temp, BRW_REGISTER_TYPE_F);
|
||||
|
||||
emit_pull_constant_load_reg(dst_reg(temp_float),
|
||||
|
|
@ -706,7 +706,7 @@ vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
|
|||
surf_index, offset_reg, NULL, NULL);
|
||||
prog_data->base.has_ubo_pull = true;
|
||||
|
||||
packed_consts = src_reg(this, glsl_type::dvec4_type);
|
||||
packed_consts = src_reg(this, glsl_dvec4_type());
|
||||
shuffle_64bit_data(dst_reg(packed_consts), temp, false);
|
||||
}
|
||||
|
||||
|
|
@ -741,7 +741,7 @@ vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
|
|||
case nir_intrinsic_shader_clock: {
|
||||
/* We cannot do anything if there is an event, so ignore it for now */
|
||||
const src_reg shader_clock = get_timestamp();
|
||||
const enum brw_reg_type type = brw_type_for_base_type(glsl_type::uvec2_type);
|
||||
const enum brw_reg_type type = brw_type_for_base_type(glsl_uvec2_type());
|
||||
|
||||
dest = get_nir_def(instr->def, type);
|
||||
emit(MOV(dest, shader_clock));
|
||||
|
|
@ -858,9 +858,9 @@ vec4_visitor::emit_conversion_from_double(dst_reg dst, src_reg src)
|
|||
unreachable("Unknown conversion");
|
||||
}
|
||||
|
||||
dst_reg temp = dst_reg(this, glsl_type::dvec4_type);
|
||||
dst_reg temp = dst_reg(this, glsl_dvec4_type());
|
||||
emit(MOV(temp, src));
|
||||
dst_reg temp2 = dst_reg(this, glsl_type::dvec4_type);
|
||||
dst_reg temp2 = dst_reg(this, glsl_dvec4_type());
|
||||
emit(op, temp2, src_reg(temp));
|
||||
|
||||
emit(VEC4_OPCODE_PICK_LOW_32BIT, retype(temp2, dst.type), src_reg(temp2));
|
||||
|
|
@ -870,8 +870,8 @@ vec4_visitor::emit_conversion_from_double(dst_reg dst, src_reg src)
|
|||
void
|
||||
vec4_visitor::emit_conversion_to_double(dst_reg dst, src_reg src)
|
||||
{
|
||||
dst_reg tmp_dst = dst_reg(src_reg(this, glsl_type::dvec4_type));
|
||||
src_reg tmp_src = retype(src_reg(this, glsl_type::vec4_type), src.type);
|
||||
dst_reg tmp_dst = dst_reg(src_reg(this, glsl_dvec4_type()));
|
||||
src_reg tmp_src = retype(src_reg(this, glsl_vec4_type()), src.type);
|
||||
emit(MOV(dst_reg(tmp_src), src));
|
||||
emit(VEC4_OPCODE_TO_DOUBLE, tmp_dst, tmp_src);
|
||||
emit(MOV(dst, src_reg(tmp_dst)));
|
||||
|
|
@ -1267,7 +1267,7 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr)
|
|||
* XOR instruction. However, empirical experiments and Curro's reading
|
||||
* of the simulator source both indicate that it's safe.
|
||||
*/
|
||||
src_reg tmp = src_reg(this, glsl_type::ivec4_type);
|
||||
src_reg tmp = src_reg(this, glsl_ivec4_type());
|
||||
inst = emit(XOR(dst_reg(tmp), op[0], op[1]));
|
||||
inst->predicate = BRW_PREDICATE_NORMAL;
|
||||
inst->conditional_mod = BRW_CONDITIONAL_L;
|
||||
|
|
@ -1325,7 +1325,7 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr)
|
|||
break;
|
||||
|
||||
case nir_op_fceil: {
|
||||
src_reg tmp = src_reg(this, glsl_type::float_type);
|
||||
src_reg tmp = src_reg(this, glsl_float_type());
|
||||
tmp.swizzle = brw_swizzle_for_size(nir_src_num_components(instr->src[0].src));
|
||||
|
||||
op[0].negate = !op[0].negate;
|
||||
|
|
@ -1355,9 +1355,9 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr)
|
|||
|
||||
case nir_op_fquantize2f16: {
|
||||
/* See also vec4_visitor::emit_pack_half_2x16() */
|
||||
src_reg tmp16 = src_reg(this, glsl_type::uvec4_type);
|
||||
src_reg tmp32 = src_reg(this, glsl_type::vec4_type);
|
||||
src_reg zero = src_reg(this, glsl_type::vec4_type);
|
||||
src_reg tmp16 = src_reg(this, glsl_uvec4_type());
|
||||
src_reg tmp32 = src_reg(this, glsl_vec4_type());
|
||||
src_reg zero = src_reg(this, glsl_vec4_type());
|
||||
|
||||
/* Check for denormal */
|
||||
src_reg abs_src0 = op[0];
|
||||
|
|
@ -1432,9 +1432,9 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr)
|
|||
* so we can then move from there to the result using align16 again
|
||||
* to honor the original writemask.
|
||||
*/
|
||||
dst_reg temp = dst_reg(this, glsl_type::dvec4_type);
|
||||
dst_reg temp = dst_reg(this, glsl_dvec4_type());
|
||||
emit(CMP(temp, op[0], op[1], conditional_mod));
|
||||
dst_reg result = dst_reg(this, glsl_type::bvec4_type);
|
||||
dst_reg result = dst_reg(this, glsl_bvec4_type());
|
||||
emit(VEC4_OPCODE_PICK_LOW_32BIT, result, src_reg(temp));
|
||||
emit(MOV(dst, src_reg(result)));
|
||||
}
|
||||
|
|
@ -1529,12 +1529,12 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr)
|
|||
unreachable("not reached");
|
||||
|
||||
case nir_op_pack_uvec2_to_uint: {
|
||||
dst_reg tmp1 = dst_reg(this, glsl_type::uint_type);
|
||||
dst_reg tmp1 = dst_reg(this, glsl_uint_type());
|
||||
tmp1.writemask = WRITEMASK_X;
|
||||
op[0].swizzle = BRW_SWIZZLE_YYYY;
|
||||
emit(SHL(tmp1, op[0], src_reg(brw_imm_ud(16u))));
|
||||
|
||||
dst_reg tmp2 = dst_reg(this, glsl_type::uint_type);
|
||||
dst_reg tmp2 = dst_reg(this, glsl_uint_type());
|
||||
tmp2.writemask = WRITEMASK_X;
|
||||
op[0].swizzle = BRW_SWIZZLE_XXXX;
|
||||
emit(AND(tmp2, op[0], src_reg(brw_imm_ud(0xffffu))));
|
||||
|
|
@ -1544,8 +1544,8 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr)
|
|||
}
|
||||
|
||||
case nir_op_pack_64_2x32_split: {
|
||||
dst_reg result = dst_reg(this, glsl_type::dvec4_type);
|
||||
dst_reg tmp = dst_reg(this, glsl_type::uvec4_type);
|
||||
dst_reg result = dst_reg(this, glsl_dvec4_type());
|
||||
dst_reg tmp = dst_reg(this, glsl_uvec4_type());
|
||||
emit(MOV(tmp, retype(op[0], BRW_REGISTER_TYPE_UD)));
|
||||
emit(VEC4_OPCODE_SET_LOW_32BIT, result, src_reg(tmp));
|
||||
emit(MOV(tmp, retype(op[1], BRW_REGISTER_TYPE_UD)));
|
||||
|
|
@ -1558,9 +1558,9 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr)
|
|||
case nir_op_unpack_64_2x32_split_y: {
|
||||
enum opcode oper = (instr->op == nir_op_unpack_64_2x32_split_x) ?
|
||||
VEC4_OPCODE_PICK_LOW_32BIT : VEC4_OPCODE_PICK_HIGH_32BIT;
|
||||
dst_reg tmp = dst_reg(this, glsl_type::dvec4_type);
|
||||
dst_reg tmp = dst_reg(this, glsl_dvec4_type());
|
||||
emit(MOV(tmp, op[0]));
|
||||
dst_reg tmp2 = dst_reg(this, glsl_type::uvec4_type);
|
||||
dst_reg tmp2 = dst_reg(this, glsl_uvec4_type());
|
||||
emit(oper, tmp2, src_reg(tmp));
|
||||
emit(MOV(dst, src_reg(tmp2)));
|
||||
break;
|
||||
|
|
@ -1716,7 +1716,7 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr)
|
|||
inst->conditional_mod = BRW_CONDITIONAL_NZ;
|
||||
|
||||
/* AND each high 32-bit channel with 0x80000000u */
|
||||
dst_reg tmp = dst_reg(this, glsl_type::uvec4_type);
|
||||
dst_reg tmp = dst_reg(this, glsl_uvec4_type());
|
||||
emit(VEC4_OPCODE_PICK_HIGH_32BIT, tmp, op[0]);
|
||||
emit(AND(tmp, src_reg(tmp), brw_imm_ud(0x80000000u)));
|
||||
|
||||
|
|
@ -1752,7 +1752,7 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr)
|
|||
|
||||
case nir_op_ffma:
|
||||
if (type_sz(dst.type) == 8) {
|
||||
dst_reg mul_dst = dst_reg(this, glsl_type::dvec4_type);
|
||||
dst_reg mul_dst = dst_reg(this, glsl_dvec4_type());
|
||||
emit(MUL(mul_dst, op[1], op[0]));
|
||||
inst = emit(ADD(dst, src_reg(mul_dst), op[2]));
|
||||
} else {
|
||||
|
|
@ -1832,7 +1832,7 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr)
|
|||
if (devinfo->ver <= 5 &&
|
||||
(instr->instr.pass_flags & BRW_NIR_BOOLEAN_MASK) ==
|
||||
BRW_NIR_BOOLEAN_NEEDS_RESOLVE) {
|
||||
dst_reg masked = dst_reg(this, glsl_type::int_type);
|
||||
dst_reg masked = dst_reg(this, glsl_int_type());
|
||||
masked.writemask = dst.writemask;
|
||||
emit(AND(masked, src_reg(dst), brw_imm_d(1)));
|
||||
src_reg masked_neg = src_reg(masked);
|
||||
|
|
@ -2124,7 +2124,7 @@ vec4_visitor::nir_emit_texture(nir_tex_instr *instr)
|
|||
* the whole vec4 and then mask off everything except .y
|
||||
*/
|
||||
mcs.swizzle = BRW_SWIZZLE_XXXX;
|
||||
emit(MOV(dst_reg(MRF, param_base + 1, glsl_type::uint_type, WRITEMASK_Y),
|
||||
emit(MOV(dst_reg(MRF, param_base + 1, glsl_uint_type(), WRITEMASK_Y),
|
||||
mcs));
|
||||
}
|
||||
inst->mlen++;
|
||||
|
|
@ -2168,7 +2168,7 @@ vec4_visitor::nir_emit_texture(nir_tex_instr *instr)
|
|||
shadow_comparator));
|
||||
}
|
||||
|
||||
emit(MOV(dst_reg(MRF, param_base + 1, glsl_type::ivec2_type, WRITEMASK_XY),
|
||||
emit(MOV(dst_reg(MRF, param_base + 1, glsl_ivec2_type(), WRITEMASK_XY),
|
||||
offset_value));
|
||||
inst->mlen++;
|
||||
break;
|
||||
|
|
@ -2204,7 +2204,7 @@ vec4_visitor::emit_mcs_fetch(const glsl_type *coordinate_type,
|
|||
{
|
||||
vec4_instruction *inst =
|
||||
new(mem_ctx) vec4_instruction(SHADER_OPCODE_TXF_MCS,
|
||||
dst_reg(this, glsl_type::uvec4_type));
|
||||
dst_reg(this, glsl_uvec4_type()));
|
||||
inst->base_mrf = 2;
|
||||
inst->src[1] = surface;
|
||||
inst->src[2] = brw_imm_ud(0); /* sampler */
|
||||
|
|
@ -2280,7 +2280,7 @@ vec4_visitor::shuffle_64bit_data(dst_reg dst, src_reg src, bool for_write,
|
|||
|
||||
/* Resolve swizzle in src */
|
||||
if (src.swizzle != BRW_SWIZZLE_XYZW) {
|
||||
dst_reg data = dst_reg(this, glsl_type::dvec4_type);
|
||||
dst_reg data = dst_reg(this, glsl_dvec4_type());
|
||||
bld.emit(mov_op, data, src);
|
||||
src = src_reg(data);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -74,7 +74,7 @@ vec4_tcs_visitor::setup_payload()
|
|||
void
|
||||
vec4_tcs_visitor::emit_prolog()
|
||||
{
|
||||
invocation_id = src_reg(this, glsl_type::uint_type);
|
||||
invocation_id = src_reg(this, glsl_uint_type());
|
||||
emit(TCS_OPCODE_GET_INSTANCE_ID, dst_reg(invocation_id));
|
||||
|
||||
/* HS threads are dispatched with the dispatch mask set to 0xFF.
|
||||
|
|
@ -113,7 +113,7 @@ vec4_tcs_visitor::emit_thread_end()
|
|||
* using the input URB handles.
|
||||
*/
|
||||
if (tcs_prog_data->instances > 1) {
|
||||
dst_reg header = dst_reg(this, glsl_type::uvec4_type);
|
||||
dst_reg header = dst_reg(this, glsl_uvec4_type());
|
||||
emit(TCS_OPCODE_CREATE_BARRIER_HEADER, header);
|
||||
emit(SHADER_OPCODE_BARRIER, dst_null_ud(), src_reg(header));
|
||||
}
|
||||
|
|
@ -135,7 +135,7 @@ vec4_tcs_visitor::emit_thread_end()
|
|||
*/
|
||||
const bool is_unpaired = i == key->input_vertices - 1;
|
||||
|
||||
dst_reg header(this, glsl_type::uvec4_type);
|
||||
dst_reg header(this, glsl_uvec4_type());
|
||||
emit(TCS_OPCODE_RELEASE_INPUT, header, brw_imm_ud(i),
|
||||
brw_imm_ud(is_unpaired));
|
||||
}
|
||||
|
|
@ -156,11 +156,11 @@ vec4_tcs_visitor::emit_input_urb_read(const dst_reg &dst,
|
|||
const src_reg &indirect_offset)
|
||||
{
|
||||
vec4_instruction *inst;
|
||||
dst_reg temp(this, glsl_type::ivec4_type);
|
||||
dst_reg temp(this, glsl_ivec4_type());
|
||||
temp.type = dst.type;
|
||||
|
||||
/* Set up the message header to reference the proper parts of the URB */
|
||||
dst_reg header = dst_reg(this, glsl_type::uvec4_type);
|
||||
dst_reg header = dst_reg(this, glsl_uvec4_type());
|
||||
inst = emit(VEC4_TCS_OPCODE_SET_INPUT_URB_OFFSETS, header, vertex_index,
|
||||
indirect_offset);
|
||||
inst->force_writemask_all = true;
|
||||
|
|
@ -193,7 +193,7 @@ vec4_tcs_visitor::emit_output_urb_read(const dst_reg &dst,
|
|||
vec4_instruction *inst;
|
||||
|
||||
/* Set up the message header to reference the proper parts of the URB */
|
||||
dst_reg header = dst_reg(this, glsl_type::uvec4_type);
|
||||
dst_reg header = dst_reg(this, glsl_uvec4_type());
|
||||
inst = emit(VEC4_TCS_OPCODE_SET_OUTPUT_URB_OFFSETS, header,
|
||||
brw_imm_ud(dst.writemask << first_component), indirect_offset);
|
||||
inst->force_writemask_all = true;
|
||||
|
|
@ -205,7 +205,7 @@ vec4_tcs_visitor::emit_output_urb_read(const dst_reg &dst,
|
|||
|
||||
if (first_component) {
|
||||
/* Read into a temporary and copy with a swizzle and writemask. */
|
||||
read->dst = retype(dst_reg(this, glsl_type::ivec4_type), dst.type);
|
||||
read->dst = retype(dst_reg(this, glsl_ivec4_type()), dst.type);
|
||||
emit(MOV(dst, swizzle(src_reg(read->dst),
|
||||
BRW_SWZ_COMP_INPUT(first_component))));
|
||||
}
|
||||
|
|
@ -220,7 +220,7 @@ vec4_tcs_visitor::emit_urb_write(const src_reg &value,
|
|||
if (writemask == 0)
|
||||
return;
|
||||
|
||||
src_reg message(this, glsl_type::uvec4_type, 2);
|
||||
src_reg message(this, glsl_uvec4_type(), 2);
|
||||
vec4_instruction *inst;
|
||||
|
||||
inst = emit(VEC4_TCS_OPCODE_SET_OUTPUT_URB_OFFSETS, dst_reg(message),
|
||||
|
|
@ -308,7 +308,7 @@ vec4_tcs_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
|
|||
if (nir_intrinsic_memory_scope(instr) != SCOPE_NONE)
|
||||
vec4_visitor::nir_emit_intrinsic(instr);
|
||||
if (nir_intrinsic_execution_scope(instr) == SCOPE_WORKGROUP) {
|
||||
dst_reg header = dst_reg(this, glsl_type::uvec4_type);
|
||||
dst_reg header = dst_reg(this, glsl_uvec4_type());
|
||||
emit(TCS_OPCODE_CREATE_BARRIER_HEADER, header);
|
||||
emit(SHADER_OPCODE_BARRIER, dst_null_ud(), src_reg(header));
|
||||
}
|
||||
|
|
|
|||
|
|
@ -82,7 +82,7 @@ vec4_tes_visitor::setup_payload()
|
|||
void
|
||||
vec4_tes_visitor::emit_prolog()
|
||||
{
|
||||
input_read_header = src_reg(this, glsl_type::uvec4_type);
|
||||
input_read_header = src_reg(this, glsl_uvec4_type());
|
||||
emit(TES_OPCODE_CREATE_INPUT_READ_HEADER, dst_reg(input_read_header));
|
||||
|
||||
this->current_annotation = NULL;
|
||||
|
|
@ -124,22 +124,22 @@ vec4_tes_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
|
|||
case nir_intrinsic_load_tess_level_outer:
|
||||
if (tes_prog_data->domain == BRW_TESS_DOMAIN_ISOLINE) {
|
||||
emit(MOV(get_nir_def(instr->def, BRW_REGISTER_TYPE_F),
|
||||
swizzle(src_reg(ATTR, 1, glsl_type::vec4_type),
|
||||
swizzle(src_reg(ATTR, 1, glsl_vec4_type()),
|
||||
BRW_SWIZZLE_ZWZW)));
|
||||
} else {
|
||||
emit(MOV(get_nir_def(instr->def, BRW_REGISTER_TYPE_F),
|
||||
swizzle(src_reg(ATTR, 1, glsl_type::vec4_type),
|
||||
swizzle(src_reg(ATTR, 1, glsl_vec4_type()),
|
||||
BRW_SWIZZLE_WZYX)));
|
||||
}
|
||||
break;
|
||||
case nir_intrinsic_load_tess_level_inner:
|
||||
if (tes_prog_data->domain == BRW_TESS_DOMAIN_QUAD) {
|
||||
emit(MOV(get_nir_def(instr->def, BRW_REGISTER_TYPE_F),
|
||||
swizzle(src_reg(ATTR, 0, glsl_type::vec4_type),
|
||||
swizzle(src_reg(ATTR, 0, glsl_vec4_type()),
|
||||
BRW_SWIZZLE_WZYX)));
|
||||
} else {
|
||||
emit(MOV(get_nir_def(instr->def, BRW_REGISTER_TYPE_F),
|
||||
src_reg(ATTR, 1, glsl_type::float_type)));
|
||||
src_reg(ATTR, 1, glsl_float_type())));
|
||||
}
|
||||
break;
|
||||
case nir_intrinsic_load_primitive_id:
|
||||
|
|
@ -156,7 +156,7 @@ vec4_tes_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
|
|||
unsigned first_component = nir_intrinsic_component(instr);
|
||||
|
||||
if (indirect_offset.file != BAD_FILE) {
|
||||
src_reg clamped_indirect_offset = src_reg(this, glsl_type::uvec4_type);
|
||||
src_reg clamped_indirect_offset = src_reg(this, glsl_uvec4_type());
|
||||
|
||||
/* Page 190 of "Volume 7: 3D Media GPGPU Engine (Haswell)" says the
|
||||
* valid range of the offset is [0, 0FFFFFFFh].
|
||||
|
|
@ -166,7 +166,7 @@ vec4_tes_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
|
|||
retype(indirect_offset, BRW_REGISTER_TYPE_UD),
|
||||
brw_imm_ud(0x0fffffffu));
|
||||
|
||||
header = src_reg(this, glsl_type::uvec4_type);
|
||||
header = src_reg(this, glsl_uvec4_type());
|
||||
emit(TES_OPCODE_ADD_INDIRECT_URB_OFFSET, dst_reg(header),
|
||||
input_read_header, clamped_indirect_offset);
|
||||
} else {
|
||||
|
|
@ -175,7 +175,7 @@ vec4_tes_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
|
|||
*/
|
||||
const unsigned max_push_slots = 24;
|
||||
if (imm_offset < max_push_slots) {
|
||||
src_reg src = src_reg(ATTR, imm_offset, glsl_type::ivec4_type);
|
||||
src_reg src = src_reg(ATTR, imm_offset, glsl_ivec4_type());
|
||||
src.swizzle = BRW_SWZ_COMP_INPUT(first_component);
|
||||
|
||||
emit(MOV(get_nir_def(instr->def, BRW_REGISTER_TYPE_D), src));
|
||||
|
|
@ -187,7 +187,7 @@ vec4_tes_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
|
|||
}
|
||||
}
|
||||
|
||||
dst_reg temp(this, glsl_type::ivec4_type);
|
||||
dst_reg temp(this, glsl_ivec4_type());
|
||||
vec4_instruction *read =
|
||||
emit(VEC4_OPCODE_URB_READ, temp, src_reg(header));
|
||||
read->offset = imm_offset;
|
||||
|
|
|
|||
|
|
@ -300,7 +300,7 @@ vec4_visitor::fix_3src_operand(const src_reg &src)
|
|||
if (src.file == UNIFORM && brw_is_single_value_swizzle(src.swizzle))
|
||||
return src;
|
||||
|
||||
dst_reg expanded = dst_reg(this, glsl_type::vec4_type);
|
||||
dst_reg expanded = dst_reg(this, glsl_vec4_type());
|
||||
expanded.type = src.type;
|
||||
emit(VEC4_OPCODE_UNPACK_UNIFORM, expanded, src);
|
||||
return src_reg(expanded);
|
||||
|
|
@ -326,7 +326,7 @@ vec4_visitor::fix_math_operand(const src_reg &src)
|
|||
if (devinfo->ver == 7 && src.file != IMM)
|
||||
return src;
|
||||
|
||||
dst_reg expanded = dst_reg(this, glsl_type::vec4_type);
|
||||
dst_reg expanded = dst_reg(this, glsl_vec4_type());
|
||||
expanded.type = src.type;
|
||||
emit(MOV(expanded, src));
|
||||
return src_reg(expanded);
|
||||
|
|
@ -342,7 +342,7 @@ vec4_visitor::emit_math(enum opcode opcode,
|
|||
|
||||
if (devinfo->ver == 6 && dst.writemask != WRITEMASK_XYZW) {
|
||||
/* MATH on Gfx6 must be align1, so we can't do writemasks. */
|
||||
math->dst = dst_reg(this, glsl_type::vec4_type);
|
||||
math->dst = dst_reg(this, glsl_vec4_type());
|
||||
math->dst.type = dst.type;
|
||||
math = emit(MOV(dst, src_reg(math->dst)));
|
||||
} else if (devinfo->ver < 6) {
|
||||
|
|
@ -390,7 +390,7 @@ vec4_visitor::emit_pack_half_2x16(dst_reg dst, src_reg src0)
|
|||
* in that the upper word of each destination channel is cleared to 0.
|
||||
*/
|
||||
|
||||
dst_reg tmp_dst(this, glsl_type::uvec2_type);
|
||||
dst_reg tmp_dst(this, glsl_uvec2_type());
|
||||
src_reg tmp_src(tmp_dst);
|
||||
|
||||
#if 0
|
||||
|
|
@ -455,7 +455,7 @@ vec4_visitor::emit_unpack_half_2x16(dst_reg dst, src_reg src0)
|
|||
* emit f16to32 in align16 mode with UD as source data type.
|
||||
*/
|
||||
|
||||
dst_reg tmp_dst(this, glsl_type::uvec2_type);
|
||||
dst_reg tmp_dst(this, glsl_uvec2_type());
|
||||
src_reg tmp_src(tmp_dst);
|
||||
|
||||
tmp_dst.writemask = WRITEMASK_X;
|
||||
|
|
@ -476,15 +476,15 @@ vec4_visitor::emit_unpack_unorm_4x8(const dst_reg &dst, src_reg src0)
|
|||
* is not suitable to generate the shift values, but we can use the packed
|
||||
* vector float and a type-converting MOV.
|
||||
*/
|
||||
dst_reg shift(this, glsl_type::uvec4_type);
|
||||
dst_reg shift(this, glsl_uvec4_type());
|
||||
emit(MOV(shift, brw_imm_vf4(0x00, 0x60, 0x70, 0x78)));
|
||||
|
||||
dst_reg shifted(this, glsl_type::uvec4_type);
|
||||
dst_reg shifted(this, glsl_uvec4_type());
|
||||
src0.swizzle = BRW_SWIZZLE_XXXX;
|
||||
emit(SHR(shifted, src0, src_reg(shift)));
|
||||
|
||||
shifted.type = BRW_REGISTER_TYPE_UB;
|
||||
dst_reg f(this, glsl_type::vec4_type);
|
||||
dst_reg f(this, glsl_vec4_type());
|
||||
emit(VEC4_OPCODE_MOV_BYTES, f, src_reg(shifted));
|
||||
|
||||
emit(MUL(dst, src_reg(f), brw_imm_f(1.0f / 255.0f)));
|
||||
|
|
@ -498,21 +498,21 @@ vec4_visitor::emit_unpack_snorm_4x8(const dst_reg &dst, src_reg src0)
|
|||
* is not suitable to generate the shift values, but we can use the packed
|
||||
* vector float and a type-converting MOV.
|
||||
*/
|
||||
dst_reg shift(this, glsl_type::uvec4_type);
|
||||
dst_reg shift(this, glsl_uvec4_type());
|
||||
emit(MOV(shift, brw_imm_vf4(0x00, 0x60, 0x70, 0x78)));
|
||||
|
||||
dst_reg shifted(this, glsl_type::uvec4_type);
|
||||
dst_reg shifted(this, glsl_uvec4_type());
|
||||
src0.swizzle = BRW_SWIZZLE_XXXX;
|
||||
emit(SHR(shifted, src0, src_reg(shift)));
|
||||
|
||||
shifted.type = BRW_REGISTER_TYPE_B;
|
||||
dst_reg f(this, glsl_type::vec4_type);
|
||||
dst_reg f(this, glsl_vec4_type());
|
||||
emit(VEC4_OPCODE_MOV_BYTES, f, src_reg(shifted));
|
||||
|
||||
dst_reg scaled(this, glsl_type::vec4_type);
|
||||
dst_reg scaled(this, glsl_vec4_type());
|
||||
emit(MUL(scaled, src_reg(f), brw_imm_f(1.0f / 127.0f)));
|
||||
|
||||
dst_reg max(this, glsl_type::vec4_type);
|
||||
dst_reg max(this, glsl_vec4_type());
|
||||
emit_minmax(BRW_CONDITIONAL_GE, max, src_reg(scaled), brw_imm_f(-1.0f));
|
||||
emit_minmax(BRW_CONDITIONAL_L, dst, src_reg(max), brw_imm_f(1.0f));
|
||||
}
|
||||
|
|
@ -520,17 +520,17 @@ vec4_visitor::emit_unpack_snorm_4x8(const dst_reg &dst, src_reg src0)
|
|||
void
|
||||
vec4_visitor::emit_pack_unorm_4x8(const dst_reg &dst, const src_reg &src0)
|
||||
{
|
||||
dst_reg saturated(this, glsl_type::vec4_type);
|
||||
dst_reg saturated(this, glsl_vec4_type());
|
||||
vec4_instruction *inst = emit(MOV(saturated, src0));
|
||||
inst->saturate = true;
|
||||
|
||||
dst_reg scaled(this, glsl_type::vec4_type);
|
||||
dst_reg scaled(this, glsl_vec4_type());
|
||||
emit(MUL(scaled, src_reg(saturated), brw_imm_f(255.0f)));
|
||||
|
||||
dst_reg rounded(this, glsl_type::vec4_type);
|
||||
dst_reg rounded(this, glsl_vec4_type());
|
||||
emit(RNDE(rounded, src_reg(scaled)));
|
||||
|
||||
dst_reg u(this, glsl_type::uvec4_type);
|
||||
dst_reg u(this, glsl_uvec4_type());
|
||||
emit(MOV(u, src_reg(rounded)));
|
||||
|
||||
src_reg bytes(u);
|
||||
|
|
@ -540,19 +540,19 @@ vec4_visitor::emit_pack_unorm_4x8(const dst_reg &dst, const src_reg &src0)
|
|||
void
|
||||
vec4_visitor::emit_pack_snorm_4x8(const dst_reg &dst, const src_reg &src0)
|
||||
{
|
||||
dst_reg max(this, glsl_type::vec4_type);
|
||||
dst_reg max(this, glsl_vec4_type());
|
||||
emit_minmax(BRW_CONDITIONAL_GE, max, src0, brw_imm_f(-1.0f));
|
||||
|
||||
dst_reg min(this, glsl_type::vec4_type);
|
||||
dst_reg min(this, glsl_vec4_type());
|
||||
emit_minmax(BRW_CONDITIONAL_L, min, src_reg(max), brw_imm_f(1.0f));
|
||||
|
||||
dst_reg scaled(this, glsl_type::vec4_type);
|
||||
dst_reg scaled(this, glsl_vec4_type());
|
||||
emit(MUL(scaled, src_reg(min), brw_imm_f(127.0f)));
|
||||
|
||||
dst_reg rounded(this, glsl_type::vec4_type);
|
||||
dst_reg rounded(this, glsl_vec4_type());
|
||||
emit(RNDE(rounded, src_reg(scaled)));
|
||||
|
||||
dst_reg i(this, glsl_type::ivec4_type);
|
||||
dst_reg i(this, glsl_ivec4_type());
|
||||
emit(MOV(i, src_reg(rounded)));
|
||||
|
||||
src_reg bytes(i);
|
||||
|
|
@ -743,7 +743,7 @@ vec4_visitor::emit_pull_constant_load_reg(dst_reg dst,
|
|||
vec4_instruction *pull;
|
||||
|
||||
if (devinfo->ver >= 7) {
|
||||
dst_reg grf_offset = dst_reg(this, glsl_type::uint_type);
|
||||
dst_reg grf_offset = dst_reg(this, glsl_uint_type());
|
||||
|
||||
grf_offset.type = offset_reg.type;
|
||||
|
||||
|
|
@ -777,8 +777,8 @@ vec4_visitor::emit_pull_constant_load_reg(dst_reg dst,
|
|||
src_reg
|
||||
vec4_visitor::emit_uniformize(const src_reg &src)
|
||||
{
|
||||
const src_reg chan_index(this, glsl_type::uint_type);
|
||||
const dst_reg dst = retype(dst_reg(this, glsl_type::uint_type),
|
||||
const src_reg chan_index(this, glsl_uint_type());
|
||||
const dst_reg dst = retype(dst_reg(this, glsl_uint_type()),
|
||||
src.type);
|
||||
|
||||
emit(SHADER_OPCODE_FIND_LIVE_CHANNEL, dst_reg(chan_index))
|
||||
|
|
@ -811,7 +811,7 @@ vec4_visitor::emit_ndc_computation()
|
|||
src_reg pos = src_reg(output_reg[VARYING_SLOT_POS][0]);
|
||||
|
||||
/* Build ndc coords, which are (x/w, y/w, z/w, 1/w) */
|
||||
dst_reg ndc = dst_reg(this, glsl_type::vec4_type);
|
||||
dst_reg ndc = dst_reg(this, glsl_vec4_type());
|
||||
output_reg[BRW_VARYING_SLOT_NDC][0] = ndc;
|
||||
output_num_components[BRW_VARYING_SLOT_NDC][0] = 4;
|
||||
|
||||
|
|
@ -835,7 +835,7 @@ vec4_visitor::emit_psiz_and_flags(dst_reg reg)
|
|||
((prog_data->vue_map.slots_valid & VARYING_BIT_PSIZ) ||
|
||||
output_reg[VARYING_SLOT_CLIP_DIST0][0].file != BAD_FILE ||
|
||||
devinfo->has_negative_rhw_bug)) {
|
||||
dst_reg header1 = dst_reg(this, glsl_type::uvec4_type);
|
||||
dst_reg header1 = dst_reg(this, glsl_uvec4_type());
|
||||
dst_reg header1_w = header1;
|
||||
header1_w.writemask = WRITEMASK_W;
|
||||
|
||||
|
|
@ -851,7 +851,7 @@ vec4_visitor::emit_psiz_and_flags(dst_reg reg)
|
|||
|
||||
if (output_reg[VARYING_SLOT_CLIP_DIST0][0].file != BAD_FILE) {
|
||||
current_annotation = "Clipping flags";
|
||||
dst_reg flags0 = dst_reg(this, glsl_type::uint_type);
|
||||
dst_reg flags0 = dst_reg(this, glsl_uint_type());
|
||||
|
||||
emit(CMP(dst_null_f(), src_reg(output_reg[VARYING_SLOT_CLIP_DIST0][0]), brw_imm_f(0.0f), BRW_CONDITIONAL_L));
|
||||
emit(VS_OPCODE_UNPACK_FLAGS_SIMD4X2, flags0, brw_imm_d(0));
|
||||
|
|
@ -859,7 +859,7 @@ vec4_visitor::emit_psiz_and_flags(dst_reg reg)
|
|||
}
|
||||
|
||||
if (output_reg[VARYING_SLOT_CLIP_DIST1][0].file != BAD_FILE) {
|
||||
dst_reg flags1 = dst_reg(this, glsl_type::uint_type);
|
||||
dst_reg flags1 = dst_reg(this, glsl_uint_type());
|
||||
emit(CMP(dst_null_f(), src_reg(output_reg[VARYING_SLOT_CLIP_DIST1][0]), brw_imm_f(0.0f), BRW_CONDITIONAL_L));
|
||||
emit(VS_OPCODE_UNPACK_FLAGS_SIMD4X2, flags1, brw_imm_d(0));
|
||||
emit(SHL(flags1, src_reg(flags1), brw_imm_d(4)));
|
||||
|
|
@ -1087,7 +1087,7 @@ vec4_visitor::get_scratch_offset(bblock_t *block, vec4_instruction *inst,
|
|||
* is in units of 16 bytes and is used to select the low/high 16-byte
|
||||
* chunk of a full dvec4, so we don't want to multiply that part.
|
||||
*/
|
||||
src_reg index = src_reg(this, glsl_type::int_type);
|
||||
src_reg index = src_reg(this, glsl_int_type());
|
||||
if (type_sz(inst->dst.type) < 8) {
|
||||
emit_before(block, inst, ADD(dst_reg(index), *reladdr,
|
||||
brw_imm_d(reg_offset)));
|
||||
|
|
@ -1124,7 +1124,7 @@ vec4_visitor::emit_scratch_read(bblock_t *block, vec4_instruction *inst,
|
|||
if (type_sz(orig_src.type) < 8) {
|
||||
emit_before(block, inst, SCRATCH_READ(temp, index));
|
||||
} else {
|
||||
dst_reg shuffled = dst_reg(this, glsl_type::dvec4_type);
|
||||
dst_reg shuffled = dst_reg(this, glsl_dvec4_type());
|
||||
dst_reg shuffled_float = retype(shuffled, BRW_REGISTER_TYPE_F);
|
||||
emit_before(block, inst, SCRATCH_READ(shuffled_float, index));
|
||||
index = get_scratch_offset(block, inst, orig_src.reladdr, reg_offset + 1);
|
||||
|
|
@ -1159,7 +1159,7 @@ vec4_visitor::emit_scratch_write(bblock_t *block, vec4_instruction *inst,
|
|||
*/
|
||||
bool is_64bit = type_sz(inst->dst.type) == 8;
|
||||
const glsl_type *alloc_type =
|
||||
is_64bit ? glsl_type::dvec4_type : glsl_type::vec4_type;
|
||||
is_64bit ? glsl_dvec4_type() : glsl_vec4_type();
|
||||
const src_reg temp = swizzle(retype(src_reg(this, alloc_type),
|
||||
inst->dst.type),
|
||||
brw_swizzle_for_mask(inst->dst.writemask));
|
||||
|
|
@ -1245,7 +1245,7 @@ vec4_visitor::emit_resolve_reladdr(int scratch_loc[], bblock_t *block,
|
|||
/* Now handle scratch access on src */
|
||||
if (src.file == VGRF && scratch_loc[src.nr] != -1) {
|
||||
dst_reg temp = dst_reg(this, type_sz(src.type) == 8 ?
|
||||
glsl_type::dvec4_type : glsl_type::vec4_type);
|
||||
glsl_dvec4_type() : glsl_vec4_type());
|
||||
emit_scratch_read(block, inst, temp, src, scratch_loc[src.nr]);
|
||||
src.nr = temp.nr;
|
||||
src.offset %= REG_SIZE;
|
||||
|
|
@ -1342,7 +1342,7 @@ vec4_visitor::resolve_ud_negate(src_reg *reg)
|
|||
!reg->negate)
|
||||
return;
|
||||
|
||||
src_reg temp = src_reg(this, glsl_type::uvec4_type);
|
||||
src_reg temp = src_reg(this, glsl_uvec4_type());
|
||||
emit(BRW_OPCODE_MOV, dst_reg(temp), *reg);
|
||||
*reg = temp;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -63,10 +63,10 @@ gfx6_gs_visitor::emit_prolog()
|
|||
*/
|
||||
this->current_annotation = "gfx6 prolog";
|
||||
this->vertex_output = src_reg(this,
|
||||
glsl_type::uint_type,
|
||||
glsl_uint_type(),
|
||||
(prog_data->vue_map.num_slots + 1) *
|
||||
nir->info.gs.vertices_out);
|
||||
this->vertex_output_offset = src_reg(this, glsl_type::uint_type);
|
||||
this->vertex_output_offset = src_reg(this, glsl_uint_type());
|
||||
emit(MOV(dst_reg(this->vertex_output_offset), brw_imm_ud(0u)));
|
||||
|
||||
/* MRF 1 will be the header for all messages (FF_SYNC and URB_WRITES),
|
||||
|
|
@ -80,7 +80,7 @@ gfx6_gs_visitor::emit_prolog()
|
|||
/* This will be used as a temporary to store writeback data of FF_SYNC
|
||||
* and URB_WRITE messages.
|
||||
*/
|
||||
this->temp = src_reg(this, glsl_type::uint_type);
|
||||
this->temp = src_reg(this, glsl_uint_type());
|
||||
|
||||
/* This will be used to know when we are processing the first vertex of
|
||||
* a primitive. We will set this to URB_WRITE_PRIM_START only when we know
|
||||
|
|
@ -88,24 +88,24 @@ gfx6_gs_visitor::emit_prolog()
|
|||
* otherwise. This way we can use its value directly in the URB write
|
||||
* headers.
|
||||
*/
|
||||
this->first_vertex = src_reg(this, glsl_type::uint_type);
|
||||
this->first_vertex = src_reg(this, glsl_uint_type());
|
||||
emit(MOV(dst_reg(this->first_vertex), brw_imm_ud(URB_WRITE_PRIM_START)));
|
||||
|
||||
/* The FF_SYNC message requires to know the number of primitives generated,
|
||||
* so keep a counter for this.
|
||||
*/
|
||||
this->prim_count = src_reg(this, glsl_type::uint_type);
|
||||
this->prim_count = src_reg(this, glsl_uint_type());
|
||||
emit(MOV(dst_reg(this->prim_count), brw_imm_ud(0u)));
|
||||
|
||||
if (gs_prog_data->num_transform_feedback_bindings) {
|
||||
/* Create a virtual register to hold destination indices in SOL */
|
||||
this->destination_indices = src_reg(this, glsl_type::uvec4_type);
|
||||
this->destination_indices = src_reg(this, glsl_uvec4_type());
|
||||
/* Create a virtual register to hold number of written primitives */
|
||||
this->sol_prim_written = src_reg(this, glsl_type::uint_type);
|
||||
this->sol_prim_written = src_reg(this, glsl_uint_type());
|
||||
/* Create a virtual register to hold Streamed Vertex Buffer Indices */
|
||||
this->svbi = src_reg(this, glsl_type::uvec4_type);
|
||||
this->svbi = src_reg(this, glsl_uvec4_type());
|
||||
/* Create a virtual register to hold max values of SVBI */
|
||||
this->max_svbi = src_reg(this, glsl_type::uvec4_type);
|
||||
this->max_svbi = src_reg(this, glsl_uvec4_type());
|
||||
emit(MOV(dst_reg(this->max_svbi),
|
||||
src_reg(retype(brw_vec1_grf(1, 4), BRW_REGISTER_TYPE_UD))));
|
||||
}
|
||||
|
|
@ -160,7 +160,7 @@ gfx6_gs_visitor::gs_emit_vertex(int stream_id)
|
|||
* array. This way we only have one instruction with an array
|
||||
* destination and we only produce a single scratch write.
|
||||
*/
|
||||
dst_reg tmp = dst_reg(src_reg(this, glsl_type::uvec4_type));
|
||||
dst_reg tmp = dst_reg(src_reg(this, glsl_uvec4_type()));
|
||||
emit_urb_slot(tmp, varying);
|
||||
dst_reg dst(this->vertex_output);
|
||||
dst.reladdr = ralloc(mem_ctx, src_reg);
|
||||
|
|
@ -231,7 +231,7 @@ gfx6_gs_visitor::gs_end_primitive()
|
|||
* next vertex. So subtract 1 to modify the flags for the previous
|
||||
* vertex.
|
||||
*/
|
||||
src_reg offset(this, glsl_type::uint_type);
|
||||
src_reg offset(this, glsl_uint_type());
|
||||
emit(ADD(dst_reg(offset), this->vertex_output_offset, brw_imm_d(-1)));
|
||||
|
||||
src_reg dst(this->vertex_output);
|
||||
|
|
@ -261,7 +261,7 @@ gfx6_gs_visitor::emit_urb_write_header(int mrf)
|
|||
* vertex in vertex_output, thus we only need to add the number of output
|
||||
* slots per vertex to that offset to obtain the flags data offset.
|
||||
*/
|
||||
src_reg flags_offset(this, glsl_type::uint_type);
|
||||
src_reg flags_offset(this, glsl_uint_type());
|
||||
emit(ADD(dst_reg(flags_offset),
|
||||
this->vertex_output_offset,
|
||||
brw_imm_d(prog_data->vue_map.num_slots)));
|
||||
|
|
@ -353,7 +353,7 @@ gfx6_gs_visitor::emit_thread_end()
|
|||
|
||||
vec4_instruction *inst = NULL;
|
||||
if (gs_prog_data->num_transform_feedback_bindings) {
|
||||
src_reg sol_temp(this, glsl_type::uvec4_type);
|
||||
src_reg sol_temp(this, glsl_uvec4_type());
|
||||
emit(GS_OPCODE_FF_SYNC_SET_PRIMITIVES,
|
||||
dst_reg(this->svbi),
|
||||
this->vertex_count,
|
||||
|
|
@ -372,7 +372,7 @@ gfx6_gs_visitor::emit_thread_end()
|
|||
{
|
||||
/* Loop over all buffered vertices and emit URB write messages */
|
||||
this->current_annotation = "gfx6 thread end: urb writes init";
|
||||
src_reg vertex(this, glsl_type::uint_type);
|
||||
src_reg vertex(this, glsl_uint_type());
|
||||
emit(MOV(dst_reg(vertex), brw_imm_ud(0u)));
|
||||
emit(MOV(dst_reg(this->vertex_output_offset), brw_imm_ud(0u)));
|
||||
|
||||
|
|
@ -469,7 +469,7 @@ gfx6_gs_visitor::emit_thread_end()
|
|||
|
||||
if (gs_prog_data->num_transform_feedback_bindings) {
|
||||
/* When emitting EOT, set SONumPrimsWritten Increment Value. */
|
||||
src_reg data(this, glsl_type::uint_type);
|
||||
src_reg data(this, glsl_uint_type());
|
||||
emit(AND(dst_reg(data), this->sol_prim_written, brw_imm_ud(0xffffu)));
|
||||
emit(SHL(dst_reg(data), data, brw_imm_ud(16u)));
|
||||
emit(GS_OPCODE_SET_DWORD_2, dst_reg(MRF, base_mrf), data);
|
||||
|
|
@ -562,7 +562,7 @@ gfx6_gs_visitor::xfb_write()
|
|||
* each vertex. So we use SVBI0 for this pointer, regardless of whether
|
||||
* transform feedback is in interleaved or separate attribs mode.
|
||||
*/
|
||||
src_reg sol_temp(this, glsl_type::uvec4_type);
|
||||
src_reg sol_temp(this, glsl_uvec4_type());
|
||||
emit(ADD(dst_reg(sol_temp), this->svbi, brw_imm_ud(num_verts)));
|
||||
|
||||
/* Compare SVBI calculated number with the maximum value, which is
|
||||
|
|
@ -602,7 +602,7 @@ gfx6_gs_visitor::xfb_program(unsigned vertex, unsigned num_verts)
|
|||
{
|
||||
unsigned binding;
|
||||
unsigned num_bindings = gs_prog_data->num_transform_feedback_bindings;
|
||||
src_reg sol_temp(this, glsl_type::uvec4_type);
|
||||
src_reg sol_temp(this, glsl_uvec4_type());
|
||||
|
||||
/* Check for buffer overflow: we need room to write the complete primitive
|
||||
* (all vertices). Otherwise, avoid writing any vertices for it
|
||||
|
|
|
|||
|
|
@ -130,9 +130,9 @@ cmod_propagation(fs_visitor *v)
|
|||
|
||||
TEST_F(cmod_propagation_test, basic)
|
||||
{
|
||||
fs_reg dest = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src0 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src1 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg dest = v->vgrf(glsl_float_type());
|
||||
fs_reg src0 = v->vgrf(glsl_float_type());
|
||||
fs_reg src1 = v->vgrf(glsl_float_type());
|
||||
fs_reg zero(brw_imm_f(0.0f));
|
||||
bld.ADD(dest, src0, src1);
|
||||
bld.CMP(bld.null_reg_f(), dest, zero, BRW_CONDITIONAL_GE);
|
||||
|
|
@ -161,9 +161,9 @@ TEST_F(cmod_propagation_test, basic)
|
|||
|
||||
TEST_F(cmod_propagation_test, basic_other_flag)
|
||||
{
|
||||
fs_reg dest = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src0 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src1 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg dest = v->vgrf(glsl_float_type());
|
||||
fs_reg src0 = v->vgrf(glsl_float_type());
|
||||
fs_reg src1 = v->vgrf(glsl_float_type());
|
||||
fs_reg zero(brw_imm_f(0.0f));
|
||||
bld.ADD(dest, src0, src1);
|
||||
bld.CMP(bld.null_reg_f(), dest, zero, BRW_CONDITIONAL_GE)
|
||||
|
|
@ -194,9 +194,9 @@ TEST_F(cmod_propagation_test, basic_other_flag)
|
|||
|
||||
TEST_F(cmod_propagation_test, cmp_nonzero)
|
||||
{
|
||||
fs_reg dest = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src0 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src1 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg dest = v->vgrf(glsl_float_type());
|
||||
fs_reg src0 = v->vgrf(glsl_float_type());
|
||||
fs_reg src1 = v->vgrf(glsl_float_type());
|
||||
fs_reg nonzero(brw_imm_f(1.0f));
|
||||
bld.ADD(dest, src0, src1);
|
||||
bld.CMP(bld.null_reg_f(), dest, nonzero, BRW_CONDITIONAL_GE);
|
||||
|
|
@ -226,8 +226,8 @@ TEST_F(cmod_propagation_test, cmp_nonzero)
|
|||
|
||||
TEST_F(cmod_propagation_test, non_cmod_instruction)
|
||||
{
|
||||
fs_reg dest = v->vgrf(glsl_type::uint_type);
|
||||
fs_reg src0 = v->vgrf(glsl_type::uint_type);
|
||||
fs_reg dest = v->vgrf(glsl_uint_type());
|
||||
fs_reg src0 = v->vgrf(glsl_uint_type());
|
||||
fs_reg zero(brw_imm_ud(0u));
|
||||
bld.FBL(dest, src0);
|
||||
bld.CMP(bld.null_reg_ud(), dest, zero, BRW_CONDITIONAL_GE);
|
||||
|
|
@ -257,7 +257,7 @@ TEST_F(cmod_propagation_test, non_cmod_instruction)
|
|||
|
||||
TEST_F(cmod_propagation_test, non_cmod_livechannel)
|
||||
{
|
||||
fs_reg dest = v->vgrf(glsl_type::uint_type);
|
||||
fs_reg dest = v->vgrf(glsl_uint_type());
|
||||
fs_reg zero(brw_imm_d(0));
|
||||
bld.emit(SHADER_OPCODE_FIND_LIVE_CHANNEL, dest)->exec_size = 32;
|
||||
bld.CMP(bld.null_reg_d(), dest, zero, BRW_CONDITIONAL_Z)->exec_size = 32;
|
||||
|
|
@ -288,10 +288,10 @@ TEST_F(cmod_propagation_test, non_cmod_livechannel)
|
|||
|
||||
TEST_F(cmod_propagation_test, intervening_flag_write)
|
||||
{
|
||||
fs_reg dest = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src0 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src1 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src2 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg dest = v->vgrf(glsl_float_type());
|
||||
fs_reg src0 = v->vgrf(glsl_float_type());
|
||||
fs_reg src1 = v->vgrf(glsl_float_type());
|
||||
fs_reg src2 = v->vgrf(glsl_float_type());
|
||||
fs_reg zero(brw_imm_f(0.0f));
|
||||
bld.ADD(dest, src0, src1);
|
||||
bld.CMP(bld.null_reg_f(), src2, zero, BRW_CONDITIONAL_GE);
|
||||
|
|
@ -325,10 +325,10 @@ TEST_F(cmod_propagation_test, intervening_flag_write)
|
|||
|
||||
TEST_F(cmod_propagation_test, intervening_mismatch_flag_write)
|
||||
{
|
||||
fs_reg dest = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src0 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src1 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src2 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg dest = v->vgrf(glsl_float_type());
|
||||
fs_reg src0 = v->vgrf(glsl_float_type());
|
||||
fs_reg src1 = v->vgrf(glsl_float_type());
|
||||
fs_reg src2 = v->vgrf(glsl_float_type());
|
||||
fs_reg zero(brw_imm_f(0.0f));
|
||||
bld.ADD(dest, src0, src1);
|
||||
bld.CMP(bld.null_reg_f(), src2, zero, BRW_CONDITIONAL_GE)
|
||||
|
|
@ -365,11 +365,11 @@ TEST_F(cmod_propagation_test, intervening_mismatch_flag_write)
|
|||
|
||||
TEST_F(cmod_propagation_test, intervening_flag_read)
|
||||
{
|
||||
fs_reg dest0 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg dest1 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src0 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src1 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src2 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg dest0 = v->vgrf(glsl_float_type());
|
||||
fs_reg dest1 = v->vgrf(glsl_float_type());
|
||||
fs_reg src0 = v->vgrf(glsl_float_type());
|
||||
fs_reg src1 = v->vgrf(glsl_float_type());
|
||||
fs_reg src2 = v->vgrf(glsl_float_type());
|
||||
fs_reg zero(brw_imm_f(0.0f));
|
||||
bld.ADD(dest0, src0, src1);
|
||||
set_predicate(BRW_PREDICATE_NORMAL, bld.SEL(dest1, src2, zero));
|
||||
|
|
@ -403,11 +403,11 @@ TEST_F(cmod_propagation_test, intervening_flag_read)
|
|||
|
||||
TEST_F(cmod_propagation_test, intervening_mismatch_flag_read)
|
||||
{
|
||||
fs_reg dest0 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg dest1 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src0 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src1 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src2 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg dest0 = v->vgrf(glsl_float_type());
|
||||
fs_reg dest1 = v->vgrf(glsl_float_type());
|
||||
fs_reg src0 = v->vgrf(glsl_float_type());
|
||||
fs_reg src1 = v->vgrf(glsl_float_type());
|
||||
fs_reg src2 = v->vgrf(glsl_float_type());
|
||||
fs_reg zero(brw_imm_f(0.0f));
|
||||
bld.ADD(dest0, src0, src1);
|
||||
set_predicate(BRW_PREDICATE_NORMAL, bld.SEL(dest1, src2, zero))
|
||||
|
|
@ -444,10 +444,10 @@ TEST_F(cmod_propagation_test, intervening_mismatch_flag_read)
|
|||
|
||||
TEST_F(cmod_propagation_test, intervening_dest_write)
|
||||
{
|
||||
fs_reg dest = v->vgrf(glsl_type::vec4_type);
|
||||
fs_reg src0 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src1 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src2 = v->vgrf(glsl_type::vec2_type);
|
||||
fs_reg dest = v->vgrf(glsl_vec4_type());
|
||||
fs_reg src0 = v->vgrf(glsl_float_type());
|
||||
fs_reg src1 = v->vgrf(glsl_float_type());
|
||||
fs_reg src2 = v->vgrf(glsl_vec2_type());
|
||||
fs_reg zero(brw_imm_f(0.0f));
|
||||
bld.ADD(offset(dest, bld, 2), src0, src1);
|
||||
bld.emit(SHADER_OPCODE_TEX, dest, src2)
|
||||
|
|
@ -483,11 +483,11 @@ TEST_F(cmod_propagation_test, intervening_dest_write)
|
|||
|
||||
TEST_F(cmod_propagation_test, intervening_flag_read_same_value)
|
||||
{
|
||||
fs_reg dest0 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg dest1 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src0 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src1 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src2 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg dest0 = v->vgrf(glsl_float_type());
|
||||
fs_reg dest1 = v->vgrf(glsl_float_type());
|
||||
fs_reg src0 = v->vgrf(glsl_float_type());
|
||||
fs_reg src1 = v->vgrf(glsl_float_type());
|
||||
fs_reg src2 = v->vgrf(glsl_float_type());
|
||||
fs_reg zero(brw_imm_f(0.0f));
|
||||
set_condmod(BRW_CONDITIONAL_GE, bld.ADD(dest0, src0, src1));
|
||||
set_predicate(BRW_PREDICATE_NORMAL, bld.SEL(dest1, src2, zero));
|
||||
|
|
@ -521,9 +521,9 @@ TEST_F(cmod_propagation_test, intervening_flag_read_same_value)
|
|||
|
||||
TEST_F(cmod_propagation_test, negate)
|
||||
{
|
||||
fs_reg dest = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src0 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src1 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg dest = v->vgrf(glsl_float_type());
|
||||
fs_reg src0 = v->vgrf(glsl_float_type());
|
||||
fs_reg src1 = v->vgrf(glsl_float_type());
|
||||
fs_reg zero(brw_imm_f(0.0f));
|
||||
bld.ADD(dest, src0, src1);
|
||||
dest.negate = true;
|
||||
|
|
@ -553,9 +553,9 @@ TEST_F(cmod_propagation_test, negate)
|
|||
|
||||
TEST_F(cmod_propagation_test, movnz)
|
||||
{
|
||||
fs_reg dest = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src0 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src1 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg dest = v->vgrf(glsl_float_type());
|
||||
fs_reg src0 = v->vgrf(glsl_float_type());
|
||||
fs_reg src1 = v->vgrf(glsl_float_type());
|
||||
bld.CMP(dest, src0, src1, BRW_CONDITIONAL_GE);
|
||||
set_condmod(BRW_CONDITIONAL_NZ,
|
||||
bld.MOV(bld.null_reg_f(), dest));
|
||||
|
|
@ -584,9 +584,9 @@ TEST_F(cmod_propagation_test, movnz)
|
|||
|
||||
TEST_F(cmod_propagation_test, different_types_cmod_with_zero)
|
||||
{
|
||||
fs_reg dest = v->vgrf(glsl_type::int_type);
|
||||
fs_reg src0 = v->vgrf(glsl_type::int_type);
|
||||
fs_reg src1 = v->vgrf(glsl_type::int_type);
|
||||
fs_reg dest = v->vgrf(glsl_int_type());
|
||||
fs_reg src0 = v->vgrf(glsl_int_type());
|
||||
fs_reg src1 = v->vgrf(glsl_int_type());
|
||||
fs_reg zero(brw_imm_f(0.0f));
|
||||
bld.ADD(dest, src0, src1);
|
||||
bld.CMP(bld.null_reg_f(), retype(dest, BRW_REGISTER_TYPE_F), zero,
|
||||
|
|
@ -617,8 +617,8 @@ TEST_F(cmod_propagation_test, different_types_cmod_with_zero)
|
|||
|
||||
TEST_F(cmod_propagation_test, andnz_one)
|
||||
{
|
||||
fs_reg dest = v->vgrf(glsl_type::int_type);
|
||||
fs_reg src0 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg dest = v->vgrf(glsl_int_type());
|
||||
fs_reg src0 = v->vgrf(glsl_float_type());
|
||||
fs_reg zero(brw_imm_f(0.0f));
|
||||
fs_reg one(brw_imm_d(1));
|
||||
|
||||
|
|
@ -651,8 +651,8 @@ TEST_F(cmod_propagation_test, andnz_one)
|
|||
|
||||
TEST_F(cmod_propagation_test, andnz_non_one)
|
||||
{
|
||||
fs_reg dest = v->vgrf(glsl_type::int_type);
|
||||
fs_reg src0 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg dest = v->vgrf(glsl_int_type());
|
||||
fs_reg src0 = v->vgrf(glsl_float_type());
|
||||
fs_reg zero(brw_imm_f(0.0f));
|
||||
fs_reg nonone(brw_imm_d(38));
|
||||
|
||||
|
|
@ -685,8 +685,8 @@ TEST_F(cmod_propagation_test, andnz_non_one)
|
|||
|
||||
TEST_F(cmod_propagation_test, cmp_cmpnz)
|
||||
{
|
||||
fs_reg dst0 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src0 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg dst0 = v->vgrf(glsl_float_type());
|
||||
fs_reg src0 = v->vgrf(glsl_float_type());
|
||||
fs_reg zero(brw_imm_f(0));
|
||||
|
||||
bld.CMP(dst0, src0, zero, BRW_CONDITIONAL_NZ);
|
||||
|
|
@ -712,8 +712,8 @@ TEST_F(cmod_propagation_test, cmp_cmpnz)
|
|||
|
||||
TEST_F(cmod_propagation_test, cmp_cmpg)
|
||||
{
|
||||
fs_reg dst0 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src0 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg dst0 = v->vgrf(glsl_float_type());
|
||||
fs_reg src0 = v->vgrf(glsl_float_type());
|
||||
fs_reg zero(brw_imm_f(0));
|
||||
|
||||
bld.CMP(dst0, src0, zero, BRW_CONDITIONAL_NZ);
|
||||
|
|
@ -741,8 +741,8 @@ TEST_F(cmod_propagation_test, cmp_cmpg)
|
|||
|
||||
TEST_F(cmod_propagation_test, plnnz_cmpnz)
|
||||
{
|
||||
fs_reg dst0 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src0 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg dst0 = v->vgrf(glsl_float_type());
|
||||
fs_reg src0 = v->vgrf(glsl_float_type());
|
||||
fs_reg zero(brw_imm_f(0));
|
||||
|
||||
set_condmod(BRW_CONDITIONAL_NZ, bld.PLN(dst0, src0, zero));
|
||||
|
|
@ -768,8 +768,8 @@ TEST_F(cmod_propagation_test, plnnz_cmpnz)
|
|||
|
||||
TEST_F(cmod_propagation_test, plnnz_cmpz)
|
||||
{
|
||||
fs_reg dst0 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src0 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg dst0 = v->vgrf(glsl_float_type());
|
||||
fs_reg src0 = v->vgrf(glsl_float_type());
|
||||
fs_reg zero(brw_imm_f(0));
|
||||
|
||||
set_condmod(BRW_CONDITIONAL_NZ, bld.PLN(dst0, src0, zero));
|
||||
|
|
@ -795,9 +795,9 @@ TEST_F(cmod_propagation_test, plnnz_cmpz)
|
|||
|
||||
TEST_F(cmod_propagation_test, plnnz_sel_cmpz)
|
||||
{
|
||||
fs_reg dst0 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg dst1 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src0 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg dst0 = v->vgrf(glsl_float_type());
|
||||
fs_reg dst1 = v->vgrf(glsl_float_type());
|
||||
fs_reg src0 = v->vgrf(glsl_float_type());
|
||||
fs_reg zero(brw_imm_f(0));
|
||||
|
||||
set_condmod(BRW_CONDITIONAL_NZ, bld.PLN(dst0, src0, zero));
|
||||
|
|
@ -829,8 +829,8 @@ TEST_F(cmod_propagation_test, plnnz_sel_cmpz)
|
|||
|
||||
TEST_F(cmod_propagation_test, cmp_cmpg_D)
|
||||
{
|
||||
fs_reg dst0 = v->vgrf(glsl_type::int_type);
|
||||
fs_reg src0 = v->vgrf(glsl_type::int_type);
|
||||
fs_reg dst0 = v->vgrf(glsl_int_type());
|
||||
fs_reg src0 = v->vgrf(glsl_int_type());
|
||||
fs_reg zero(brw_imm_d(0));
|
||||
fs_reg one(brw_imm_d(1));
|
||||
|
||||
|
|
@ -859,8 +859,8 @@ TEST_F(cmod_propagation_test, cmp_cmpg_D)
|
|||
|
||||
TEST_F(cmod_propagation_test, cmp_cmpg_UD)
|
||||
{
|
||||
fs_reg dst0 = v->vgrf(glsl_type::uint_type);
|
||||
fs_reg src0 = v->vgrf(glsl_type::uint_type);
|
||||
fs_reg dst0 = v->vgrf(glsl_uint_type());
|
||||
fs_reg src0 = v->vgrf(glsl_uint_type());
|
||||
fs_reg zero(brw_imm_ud(0));
|
||||
|
||||
bld.CMP(dst0, src0, zero, BRW_CONDITIONAL_NZ);
|
||||
|
|
@ -886,8 +886,8 @@ TEST_F(cmod_propagation_test, cmp_cmpg_UD)
|
|||
|
||||
TEST_F(cmod_propagation_test, cmp_cmpl_D)
|
||||
{
|
||||
fs_reg dst0 = v->vgrf(glsl_type::int_type);
|
||||
fs_reg src0 = v->vgrf(glsl_type::int_type);
|
||||
fs_reg dst0 = v->vgrf(glsl_int_type());
|
||||
fs_reg src0 = v->vgrf(glsl_int_type());
|
||||
fs_reg zero(brw_imm_d(0));
|
||||
|
||||
bld.CMP(dst0, src0, zero, BRW_CONDITIONAL_NZ);
|
||||
|
|
@ -913,8 +913,8 @@ TEST_F(cmod_propagation_test, cmp_cmpl_D)
|
|||
|
||||
TEST_F(cmod_propagation_test, cmp_cmpl_UD)
|
||||
{
|
||||
fs_reg dst0 = v->vgrf(glsl_type::uint_type);
|
||||
fs_reg src0 = v->vgrf(glsl_type::uint_type);
|
||||
fs_reg dst0 = v->vgrf(glsl_uint_type());
|
||||
fs_reg src0 = v->vgrf(glsl_uint_type());
|
||||
fs_reg zero(brw_imm_ud(0));
|
||||
|
||||
bld.CMP(dst0, src0, zero, BRW_CONDITIONAL_NZ);
|
||||
|
|
@ -942,8 +942,8 @@ TEST_F(cmod_propagation_test, cmp_cmpl_UD)
|
|||
|
||||
TEST_F(cmod_propagation_test, andz_one)
|
||||
{
|
||||
fs_reg dest = v->vgrf(glsl_type::int_type);
|
||||
fs_reg src0 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg dest = v->vgrf(glsl_int_type());
|
||||
fs_reg src0 = v->vgrf(glsl_float_type());
|
||||
fs_reg zero(brw_imm_f(0.0f));
|
||||
fs_reg one(brw_imm_d(1));
|
||||
|
||||
|
|
@ -976,9 +976,9 @@ TEST_F(cmod_propagation_test, andz_one)
|
|||
|
||||
TEST_F(cmod_propagation_test, add_not_merge_with_compare)
|
||||
{
|
||||
fs_reg dest = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src0 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src1 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg dest = v->vgrf(glsl_float_type());
|
||||
fs_reg src0 = v->vgrf(glsl_float_type());
|
||||
fs_reg src1 = v->vgrf(glsl_float_type());
|
||||
bld.ADD(dest, src0, src1);
|
||||
bld.CMP(bld.null_reg_f(), src0, src1, BRW_CONDITIONAL_L);
|
||||
|
||||
|
|
@ -1009,9 +1009,9 @@ TEST_F(cmod_propagation_test, add_not_merge_with_compare)
|
|||
|
||||
TEST_F(cmod_propagation_test, subtract_merge_with_compare)
|
||||
{
|
||||
fs_reg dest = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src0 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src1 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg dest = v->vgrf(glsl_float_type());
|
||||
fs_reg src0 = v->vgrf(glsl_float_type());
|
||||
fs_reg src1 = v->vgrf(glsl_float_type());
|
||||
bld.ADD(dest, src0, negate(src1));
|
||||
bld.CMP(bld.null_reg_f(), src0, src1, BRW_CONDITIONAL_L);
|
||||
|
||||
|
|
@ -1037,8 +1037,8 @@ TEST_F(cmod_propagation_test, subtract_merge_with_compare)
|
|||
|
||||
TEST_F(cmod_propagation_test, subtract_immediate_merge_with_compare)
|
||||
{
|
||||
fs_reg dest = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src0 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg dest = v->vgrf(glsl_float_type());
|
||||
fs_reg src0 = v->vgrf(glsl_float_type());
|
||||
fs_reg one(brw_imm_f(1.0f));
|
||||
fs_reg negative_one(brw_imm_f(-1.0f));
|
||||
|
||||
|
|
@ -1067,10 +1067,10 @@ TEST_F(cmod_propagation_test, subtract_immediate_merge_with_compare)
|
|||
|
||||
TEST_F(cmod_propagation_test, subtract_merge_with_compare_intervening_add)
|
||||
{
|
||||
fs_reg dest0 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg dest1 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src0 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src1 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg dest0 = v->vgrf(glsl_float_type());
|
||||
fs_reg dest1 = v->vgrf(glsl_float_type());
|
||||
fs_reg src0 = v->vgrf(glsl_float_type());
|
||||
fs_reg src1 = v->vgrf(glsl_float_type());
|
||||
bld.ADD(dest0, src0, negate(src1));
|
||||
bld.ADD(dest1, src0, src1);
|
||||
bld.CMP(bld.null_reg_f(), src0, src1, BRW_CONDITIONAL_L);
|
||||
|
|
@ -1101,10 +1101,10 @@ TEST_F(cmod_propagation_test, subtract_merge_with_compare_intervening_add)
|
|||
|
||||
TEST_F(cmod_propagation_test, subtract_not_merge_with_compare_intervening_partial_write)
|
||||
{
|
||||
fs_reg dest0 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg dest1 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src0 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src1 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg dest0 = v->vgrf(glsl_float_type());
|
||||
fs_reg dest1 = v->vgrf(glsl_float_type());
|
||||
fs_reg src0 = v->vgrf(glsl_float_type());
|
||||
fs_reg src1 = v->vgrf(glsl_float_type());
|
||||
bld.ADD(dest0, src0, negate(src1));
|
||||
set_predicate(BRW_PREDICATE_NORMAL, bld.ADD(dest1, src0, negate(src1)));
|
||||
bld.CMP(bld.null_reg_f(), src0, src1, BRW_CONDITIONAL_L);
|
||||
|
|
@ -1136,10 +1136,10 @@ TEST_F(cmod_propagation_test, subtract_not_merge_with_compare_intervening_partia
|
|||
|
||||
TEST_F(cmod_propagation_test, subtract_not_merge_with_compare_intervening_add)
|
||||
{
|
||||
fs_reg dest0 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg dest1 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src0 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src1 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg dest0 = v->vgrf(glsl_float_type());
|
||||
fs_reg dest1 = v->vgrf(glsl_float_type());
|
||||
fs_reg src0 = v->vgrf(glsl_float_type());
|
||||
fs_reg src1 = v->vgrf(glsl_float_type());
|
||||
bld.ADD(dest0, src0, negate(src1));
|
||||
set_condmod(BRW_CONDITIONAL_EQ, bld.ADD(dest1, src0, src1));
|
||||
bld.CMP(bld.null_reg_f(), src0, src1, BRW_CONDITIONAL_L);
|
||||
|
|
@ -1171,9 +1171,9 @@ TEST_F(cmod_propagation_test, subtract_not_merge_with_compare_intervening_add)
|
|||
|
||||
TEST_F(cmod_propagation_test, add_merge_with_compare)
|
||||
{
|
||||
fs_reg dest = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src0 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src1 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg dest = v->vgrf(glsl_float_type());
|
||||
fs_reg src0 = v->vgrf(glsl_float_type());
|
||||
fs_reg src1 = v->vgrf(glsl_float_type());
|
||||
bld.ADD(dest, src0, src1);
|
||||
bld.CMP(bld.null_reg_f(), src0, negate(src1), BRW_CONDITIONAL_L);
|
||||
|
||||
|
|
@ -1199,9 +1199,9 @@ TEST_F(cmod_propagation_test, add_merge_with_compare)
|
|||
|
||||
TEST_F(cmod_propagation_test, negative_subtract_merge_with_compare)
|
||||
{
|
||||
fs_reg dest = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src0 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src1 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg dest = v->vgrf(glsl_float_type());
|
||||
fs_reg src0 = v->vgrf(glsl_float_type());
|
||||
fs_reg src1 = v->vgrf(glsl_float_type());
|
||||
bld.ADD(dest, src1, negate(src0));
|
||||
bld.CMP(bld.null_reg_f(), src0, src1, BRW_CONDITIONAL_L);
|
||||
|
||||
|
|
@ -1230,11 +1230,11 @@ TEST_F(cmod_propagation_test, negative_subtract_merge_with_compare)
|
|||
|
||||
TEST_F(cmod_propagation_test, subtract_delete_compare)
|
||||
{
|
||||
fs_reg dest = v->vgrf(glsl_type::float_type);
|
||||
fs_reg dest1 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src0 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src1 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src2 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg dest = v->vgrf(glsl_float_type());
|
||||
fs_reg dest1 = v->vgrf(glsl_float_type());
|
||||
fs_reg src0 = v->vgrf(glsl_float_type());
|
||||
fs_reg src1 = v->vgrf(glsl_float_type());
|
||||
fs_reg src2 = v->vgrf(glsl_float_type());
|
||||
|
||||
set_condmod(BRW_CONDITIONAL_L, bld.ADD(dest, src0, negate(src1)));
|
||||
set_predicate(BRW_PREDICATE_NORMAL, bld.MOV(dest1, src2));
|
||||
|
|
@ -1269,11 +1269,11 @@ TEST_F(cmod_propagation_test, subtract_delete_compare_other_flag)
|
|||
/* This test is the same as subtract_delete_compare but it explicitly used
|
||||
* flag f0.1 for the subtraction and the comparison.
|
||||
*/
|
||||
fs_reg dest = v->vgrf(glsl_type::float_type);
|
||||
fs_reg dest1 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src0 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src1 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src2 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg dest = v->vgrf(glsl_float_type());
|
||||
fs_reg dest1 = v->vgrf(glsl_float_type());
|
||||
fs_reg src0 = v->vgrf(glsl_float_type());
|
||||
fs_reg src1 = v->vgrf(glsl_float_type());
|
||||
fs_reg src2 = v->vgrf(glsl_float_type());
|
||||
|
||||
set_condmod(BRW_CONDITIONAL_L, bld.ADD(dest, src0, negate(src1)))
|
||||
->flag_subreg = 1;
|
||||
|
|
@ -1308,9 +1308,9 @@ TEST_F(cmod_propagation_test, subtract_delete_compare_other_flag)
|
|||
|
||||
TEST_F(cmod_propagation_test, subtract_to_mismatch_flag)
|
||||
{
|
||||
fs_reg dest = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src0 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src1 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg dest = v->vgrf(glsl_float_type());
|
||||
fs_reg src0 = v->vgrf(glsl_float_type());
|
||||
fs_reg src1 = v->vgrf(glsl_float_type());
|
||||
|
||||
set_condmod(BRW_CONDITIONAL_L, bld.ADD(dest, src0, negate(src1)));
|
||||
bld.CMP(bld.null_reg_f(), src0, src1, BRW_CONDITIONAL_L)
|
||||
|
|
@ -1343,9 +1343,9 @@ TEST_F(cmod_propagation_test, subtract_to_mismatch_flag)
|
|||
TEST_F(cmod_propagation_test,
|
||||
subtract_merge_with_compare_intervening_mismatch_flag_write)
|
||||
{
|
||||
fs_reg dest0 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src0 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src1 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg dest0 = v->vgrf(glsl_float_type());
|
||||
fs_reg src0 = v->vgrf(glsl_float_type());
|
||||
fs_reg src1 = v->vgrf(glsl_float_type());
|
||||
|
||||
bld.ADD(dest0, src0, negate(src1));
|
||||
bld.CMP(bld.null_reg_f(), src0, src1, BRW_CONDITIONAL_L)
|
||||
|
|
@ -1390,11 +1390,11 @@ TEST_F(cmod_propagation_test,
|
|||
TEST_F(cmod_propagation_test,
|
||||
subtract_merge_with_compare_intervening_mismatch_flag_read)
|
||||
{
|
||||
fs_reg dest0 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg dest1 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src0 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src1 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src2 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg dest0 = v->vgrf(glsl_float_type());
|
||||
fs_reg dest1 = v->vgrf(glsl_float_type());
|
||||
fs_reg src0 = v->vgrf(glsl_float_type());
|
||||
fs_reg src1 = v->vgrf(glsl_float_type());
|
||||
fs_reg src2 = v->vgrf(glsl_float_type());
|
||||
fs_reg zero(brw_imm_f(0.0f));
|
||||
|
||||
bld.ADD(dest0, src0, negate(src1));
|
||||
|
|
@ -1430,10 +1430,10 @@ TEST_F(cmod_propagation_test,
|
|||
|
||||
TEST_F(cmod_propagation_test, subtract_delete_compare_derp)
|
||||
{
|
||||
fs_reg dest0 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg dest1 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src0 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src1 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg dest0 = v->vgrf(glsl_float_type());
|
||||
fs_reg dest1 = v->vgrf(glsl_float_type());
|
||||
fs_reg src0 = v->vgrf(glsl_float_type());
|
||||
fs_reg src1 = v->vgrf(glsl_float_type());
|
||||
|
||||
set_condmod(BRW_CONDITIONAL_L, bld.ADD(dest0, src0, negate(src1)));
|
||||
set_predicate(BRW_PREDICATE_NORMAL, bld.ADD(dest1, negate(src0), src1));
|
||||
|
|
@ -1465,8 +1465,8 @@ TEST_F(cmod_propagation_test, subtract_delete_compare_derp)
|
|||
|
||||
TEST_F(cmod_propagation_test, signed_unsigned_comparison_mismatch)
|
||||
{
|
||||
fs_reg dest0 = v->vgrf(glsl_type::int_type);
|
||||
fs_reg src0 = v->vgrf(glsl_type::int_type);
|
||||
fs_reg dest0 = v->vgrf(glsl_int_type());
|
||||
fs_reg src0 = v->vgrf(glsl_int_type());
|
||||
src0.type = BRW_REGISTER_TYPE_W;
|
||||
|
||||
bld.ASR(dest0, negate(src0), brw_imm_d(15));
|
||||
|
|
@ -2604,9 +2604,9 @@ TEST_F(cmod_propagation_test, not_to_or)
|
|||
/* Exercise propagation of conditional modifier from a NOT instruction to
|
||||
* another ALU instruction as performed by cmod_propagate_not.
|
||||
*/
|
||||
fs_reg dest = v->vgrf(glsl_type::uint_type);
|
||||
fs_reg src0 = v->vgrf(glsl_type::uint_type);
|
||||
fs_reg src1 = v->vgrf(glsl_type::uint_type);
|
||||
fs_reg dest = v->vgrf(glsl_uint_type());
|
||||
fs_reg src0 = v->vgrf(glsl_uint_type());
|
||||
fs_reg src1 = v->vgrf(glsl_uint_type());
|
||||
bld.OR(dest, src0, src1);
|
||||
set_condmod(BRW_CONDITIONAL_NZ, bld.NOT(bld.null_reg_ud(), dest));
|
||||
|
||||
|
|
@ -2637,9 +2637,9 @@ TEST_F(cmod_propagation_test, not_to_and)
|
|||
/* Exercise propagation of conditional modifier from a NOT instruction to
|
||||
* another ALU instruction as performed by cmod_propagate_not.
|
||||
*/
|
||||
fs_reg dest = v->vgrf(glsl_type::uint_type);
|
||||
fs_reg src0 = v->vgrf(glsl_type::uint_type);
|
||||
fs_reg src1 = v->vgrf(glsl_type::uint_type);
|
||||
fs_reg dest = v->vgrf(glsl_uint_type());
|
||||
fs_reg src0 = v->vgrf(glsl_uint_type());
|
||||
fs_reg src1 = v->vgrf(glsl_uint_type());
|
||||
bld.AND(dest, src0, src1);
|
||||
set_condmod(BRW_CONDITIONAL_NZ, bld.NOT(bld.null_reg_ud(), dest));
|
||||
|
||||
|
|
@ -2675,9 +2675,9 @@ TEST_F(cmod_propagation_test, not_to_uadd)
|
|||
* restriction is just the the destination type of the ALU instruction is
|
||||
* the same as the source type of the NOT instruction.
|
||||
*/
|
||||
fs_reg dest = v->vgrf(glsl_type::uint_type);
|
||||
fs_reg src0 = v->vgrf(glsl_type::uint_type);
|
||||
fs_reg src1 = v->vgrf(glsl_type::uint_type);
|
||||
fs_reg dest = v->vgrf(glsl_uint_type());
|
||||
fs_reg src0 = v->vgrf(glsl_uint_type());
|
||||
fs_reg src1 = v->vgrf(glsl_uint_type());
|
||||
bld.ADD(dest, src0, src1);
|
||||
set_condmod(BRW_CONDITIONAL_NZ, bld.NOT(bld.null_reg_ud(), dest));
|
||||
|
||||
|
|
@ -2715,9 +2715,9 @@ TEST_F(cmod_propagation_test, not_to_fadd_to_ud)
|
|||
* restriction is just the the destination type of the ALU instruction is
|
||||
* the same as the source type of the NOT instruction.
|
||||
*/
|
||||
fs_reg dest = v->vgrf(glsl_type::uint_type);
|
||||
fs_reg src0 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src1 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg dest = v->vgrf(glsl_uint_type());
|
||||
fs_reg src0 = v->vgrf(glsl_float_type());
|
||||
fs_reg src1 = v->vgrf(glsl_float_type());
|
||||
bld.ADD(dest, src0, src1);
|
||||
set_condmod(BRW_CONDITIONAL_NZ, bld.NOT(bld.null_reg_ud(), dest));
|
||||
|
||||
|
|
@ -2755,9 +2755,9 @@ TEST_F(cmod_propagation_test, not_to_fadd)
|
|||
* restriction is just the the destination type of the ALU instruction is
|
||||
* the same as the source type of the NOT instruction.
|
||||
*/
|
||||
fs_reg dest = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src0 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src1 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg dest = v->vgrf(glsl_float_type());
|
||||
fs_reg src0 = v->vgrf(glsl_float_type());
|
||||
fs_reg src1 = v->vgrf(glsl_float_type());
|
||||
bld.ADD(dest, src0, src1);
|
||||
set_condmod(BRW_CONDITIONAL_NZ,
|
||||
bld.NOT(bld.null_reg_ud(),
|
||||
|
|
@ -2792,11 +2792,11 @@ TEST_F(cmod_propagation_test, not_to_or_intervening_flag_read_compatible_value)
|
|||
/* Exercise propagation of conditional modifier from a NOT instruction to
|
||||
* another ALU instruction as performed by cmod_propagate_not.
|
||||
*/
|
||||
fs_reg dest0 = v->vgrf(glsl_type::uint_type);
|
||||
fs_reg dest1 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src0 = v->vgrf(glsl_type::uint_type);
|
||||
fs_reg src1 = v->vgrf(glsl_type::uint_type);
|
||||
fs_reg src2 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg dest0 = v->vgrf(glsl_uint_type());
|
||||
fs_reg dest1 = v->vgrf(glsl_float_type());
|
||||
fs_reg src0 = v->vgrf(glsl_uint_type());
|
||||
fs_reg src1 = v->vgrf(glsl_uint_type());
|
||||
fs_reg src2 = v->vgrf(glsl_float_type());
|
||||
fs_reg zero(brw_imm_f(0.0f));
|
||||
set_condmod(BRW_CONDITIONAL_Z, bld.OR(dest0, src0, src1));
|
||||
set_predicate(BRW_PREDICATE_NORMAL, bld.SEL(dest1, src2, zero));
|
||||
|
|
@ -2834,11 +2834,11 @@ TEST_F(cmod_propagation_test,
|
|||
/* Exercise propagation of conditional modifier from a NOT instruction to
|
||||
* another ALU instruction as performed by cmod_propagate_not.
|
||||
*/
|
||||
fs_reg dest0 = v->vgrf(glsl_type::uint_type);
|
||||
fs_reg dest1 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src0 = v->vgrf(glsl_type::uint_type);
|
||||
fs_reg src1 = v->vgrf(glsl_type::uint_type);
|
||||
fs_reg src2 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg dest0 = v->vgrf(glsl_uint_type());
|
||||
fs_reg dest1 = v->vgrf(glsl_float_type());
|
||||
fs_reg src0 = v->vgrf(glsl_uint_type());
|
||||
fs_reg src1 = v->vgrf(glsl_uint_type());
|
||||
fs_reg src2 = v->vgrf(glsl_float_type());
|
||||
fs_reg zero(brw_imm_f(0.0f));
|
||||
set_condmod(BRW_CONDITIONAL_Z, bld.OR(dest0, src0, src1))
|
||||
->flag_subreg = 1;
|
||||
|
|
@ -2879,11 +2879,11 @@ TEST_F(cmod_propagation_test, not_to_or_intervening_flag_read_incompatible_value
|
|||
/* Exercise propagation of conditional modifier from a NOT instruction to
|
||||
* another ALU instruction as performed by cmod_propagate_not.
|
||||
*/
|
||||
fs_reg dest0 = v->vgrf(glsl_type::uint_type);
|
||||
fs_reg dest1 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src0 = v->vgrf(glsl_type::uint_type);
|
||||
fs_reg src1 = v->vgrf(glsl_type::uint_type);
|
||||
fs_reg src2 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg dest0 = v->vgrf(glsl_uint_type());
|
||||
fs_reg dest1 = v->vgrf(glsl_float_type());
|
||||
fs_reg src0 = v->vgrf(glsl_uint_type());
|
||||
fs_reg src1 = v->vgrf(glsl_uint_type());
|
||||
fs_reg src2 = v->vgrf(glsl_float_type());
|
||||
fs_reg zero(brw_imm_f(0.0f));
|
||||
set_condmod(BRW_CONDITIONAL_NZ, bld.OR(dest0, src0, src1));
|
||||
set_predicate(BRW_PREDICATE_NORMAL, bld.SEL(dest1, src2, zero));
|
||||
|
|
@ -2921,10 +2921,10 @@ TEST_F(cmod_propagation_test, not_to_or_intervening_mismatch_flag_write)
|
|||
/* Exercise propagation of conditional modifier from a NOT instruction to
|
||||
* another ALU instruction as performed by cmod_propagate_not.
|
||||
*/
|
||||
fs_reg dest0 = v->vgrf(glsl_type::uint_type);
|
||||
fs_reg dest1 = v->vgrf(glsl_type::uint_type);
|
||||
fs_reg src0 = v->vgrf(glsl_type::uint_type);
|
||||
fs_reg src1 = v->vgrf(glsl_type::uint_type);
|
||||
fs_reg dest0 = v->vgrf(glsl_uint_type());
|
||||
fs_reg dest1 = v->vgrf(glsl_uint_type());
|
||||
fs_reg src0 = v->vgrf(glsl_uint_type());
|
||||
fs_reg src1 = v->vgrf(glsl_uint_type());
|
||||
|
||||
bld.OR(dest0, src0, src1);
|
||||
set_condmod(BRW_CONDITIONAL_Z, bld.OR(dest1, src0, src1))
|
||||
|
|
@ -2964,11 +2964,11 @@ TEST_F(cmod_propagation_test, not_to_or_intervening_mismatch_flag_read)
|
|||
/* Exercise propagation of conditional modifier from a NOT instruction to
|
||||
* another ALU instruction as performed by cmod_propagate_not.
|
||||
*/
|
||||
fs_reg dest0 = v->vgrf(glsl_type::uint_type);
|
||||
fs_reg dest1 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src0 = v->vgrf(glsl_type::uint_type);
|
||||
fs_reg src1 = v->vgrf(glsl_type::uint_type);
|
||||
fs_reg src2 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg dest0 = v->vgrf(glsl_uint_type());
|
||||
fs_reg dest1 = v->vgrf(glsl_float_type());
|
||||
fs_reg src0 = v->vgrf(glsl_uint_type());
|
||||
fs_reg src1 = v->vgrf(glsl_uint_type());
|
||||
fs_reg src2 = v->vgrf(glsl_float_type());
|
||||
fs_reg zero(brw_imm_f(0.0f));
|
||||
|
||||
bld.OR(dest0, src0, src1);
|
||||
|
|
@ -3006,8 +3006,8 @@ TEST_F(cmod_propagation_test, not_to_or_intervening_mismatch_flag_read)
|
|||
|
||||
TEST_F(cmod_propagation_test, cmp_to_add_float_e)
|
||||
{
|
||||
fs_reg dest = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src0 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg dest = v->vgrf(glsl_float_type());
|
||||
fs_reg src0 = v->vgrf(glsl_float_type());
|
||||
fs_reg neg10(brw_imm_f(-10.0f));
|
||||
fs_reg pos10(brw_imm_f(10.0f));
|
||||
|
||||
|
|
@ -3036,8 +3036,8 @@ TEST_F(cmod_propagation_test, cmp_to_add_float_e)
|
|||
|
||||
TEST_F(cmod_propagation_test, cmp_to_add_float_g)
|
||||
{
|
||||
fs_reg dest = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src0 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg dest = v->vgrf(glsl_float_type());
|
||||
fs_reg src0 = v->vgrf(glsl_float_type());
|
||||
fs_reg neg10(brw_imm_f(-10.0f));
|
||||
fs_reg pos10(brw_imm_f(10.0f));
|
||||
|
||||
|
|
@ -3064,8 +3064,8 @@ TEST_F(cmod_propagation_test, cmp_to_add_float_g)
|
|||
|
||||
TEST_F(cmod_propagation_test, cmp_to_add_float_le)
|
||||
{
|
||||
fs_reg dest = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src0 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg dest = v->vgrf(glsl_float_type());
|
||||
fs_reg src0 = v->vgrf(glsl_float_type());
|
||||
fs_reg neg10(brw_imm_f(-10.0f));
|
||||
fs_reg pos10(brw_imm_f(10.0f));
|
||||
|
||||
|
|
@ -3092,12 +3092,12 @@ TEST_F(cmod_propagation_test, cmp_to_add_float_le)
|
|||
|
||||
TEST_F(cmod_propagation_test, prop_across_sel_gfx7)
|
||||
{
|
||||
fs_reg dest1 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg dest2 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src0 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src1 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src2 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src3 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg dest1 = v->vgrf(glsl_float_type());
|
||||
fs_reg dest2 = v->vgrf(glsl_float_type());
|
||||
fs_reg src0 = v->vgrf(glsl_float_type());
|
||||
fs_reg src1 = v->vgrf(glsl_float_type());
|
||||
fs_reg src2 = v->vgrf(glsl_float_type());
|
||||
fs_reg src3 = v->vgrf(glsl_float_type());
|
||||
fs_reg zero(brw_imm_f(0.0f));
|
||||
bld.ADD(dest1, src0, src1);
|
||||
bld.emit_minmax(dest2, src2, src3, BRW_CONDITIONAL_GE);
|
||||
|
|
@ -3134,12 +3134,12 @@ TEST_F(cmod_propagation_test, prop_across_sel_gfx5)
|
|||
devinfo->ver = 5;
|
||||
devinfo->verx10 = devinfo->ver * 10;
|
||||
|
||||
fs_reg dest1 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg dest2 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src0 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src1 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src2 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src3 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg dest1 = v->vgrf(glsl_float_type());
|
||||
fs_reg dest2 = v->vgrf(glsl_float_type());
|
||||
fs_reg src0 = v->vgrf(glsl_float_type());
|
||||
fs_reg src1 = v->vgrf(glsl_float_type());
|
||||
fs_reg src2 = v->vgrf(glsl_float_type());
|
||||
fs_reg src3 = v->vgrf(glsl_float_type());
|
||||
fs_reg zero(brw_imm_f(0.0f));
|
||||
bld.ADD(dest1, src0, src1);
|
||||
bld.emit_minmax(dest2, src2, src3, BRW_CONDITIONAL_GE);
|
||||
|
|
@ -3182,9 +3182,9 @@ TEST_F(cmod_propagation_test, prop_into_sel_gfx5)
|
|||
devinfo->ver = 5;
|
||||
devinfo->verx10 = devinfo->ver * 10;
|
||||
|
||||
fs_reg dest = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src0 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src1 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg dest = v->vgrf(glsl_float_type());
|
||||
fs_reg src0 = v->vgrf(glsl_float_type());
|
||||
fs_reg src1 = v->vgrf(glsl_float_type());
|
||||
fs_reg zero(brw_imm_f(0.0f));
|
||||
bld.emit_minmax(dest, src0, src1, BRW_CONDITIONAL_GE);
|
||||
bld.CMP(bld.null_reg_f(), dest, zero, BRW_CONDITIONAL_GE);
|
||||
|
|
|
|||
|
|
@ -119,10 +119,10 @@ copy_propagation(fs_visitor *v)
|
|||
|
||||
TEST_F(copy_propagation_test, basic)
|
||||
{
|
||||
fs_reg vgrf0 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg vgrf1 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg vgrf2 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg vgrf3 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg vgrf0 = v->vgrf(glsl_float_type());
|
||||
fs_reg vgrf1 = v->vgrf(glsl_float_type());
|
||||
fs_reg vgrf2 = v->vgrf(glsl_float_type());
|
||||
fs_reg vgrf3 = v->vgrf(glsl_float_type());
|
||||
bld.MOV(vgrf0, vgrf2);
|
||||
bld.ADD(vgrf1, vgrf0, vgrf3);
|
||||
|
||||
|
|
@ -160,9 +160,9 @@ TEST_F(copy_propagation_test, basic)
|
|||
|
||||
TEST_F(copy_propagation_test, maxmax_sat_imm)
|
||||
{
|
||||
fs_reg vgrf0 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg vgrf1 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg vgrf2 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg vgrf0 = v->vgrf(glsl_float_type());
|
||||
fs_reg vgrf1 = v->vgrf(glsl_float_type());
|
||||
fs_reg vgrf2 = v->vgrf(glsl_float_type());
|
||||
|
||||
static const struct {
|
||||
enum brw_conditional_mod conditional_mod;
|
||||
|
|
|
|||
|
|
@ -120,10 +120,10 @@ saturate_propagation(fs_visitor *v)
|
|||
|
||||
TEST_F(saturate_propagation_test, basic)
|
||||
{
|
||||
fs_reg dst0 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg dst1 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src0 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src1 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg dst0 = v->vgrf(glsl_float_type());
|
||||
fs_reg dst1 = v->vgrf(glsl_float_type());
|
||||
fs_reg src0 = v->vgrf(glsl_float_type());
|
||||
fs_reg src1 = v->vgrf(glsl_float_type());
|
||||
bld.ADD(dst0, src0, src1);
|
||||
set_saturate(true, bld.MOV(dst1, dst0));
|
||||
|
||||
|
|
@ -154,11 +154,11 @@ TEST_F(saturate_propagation_test, basic)
|
|||
|
||||
TEST_F(saturate_propagation_test, other_non_saturated_use)
|
||||
{
|
||||
fs_reg dst0 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg dst1 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg dst2 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src0 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src1 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg dst0 = v->vgrf(glsl_float_type());
|
||||
fs_reg dst1 = v->vgrf(glsl_float_type());
|
||||
fs_reg dst2 = v->vgrf(glsl_float_type());
|
||||
fs_reg src0 = v->vgrf(glsl_float_type());
|
||||
fs_reg src1 = v->vgrf(glsl_float_type());
|
||||
bld.ADD(dst0, src0, src1);
|
||||
set_saturate(true, bld.MOV(dst1, dst0));
|
||||
bld.ADD(dst2, dst0, src0);
|
||||
|
|
@ -191,10 +191,10 @@ TEST_F(saturate_propagation_test, other_non_saturated_use)
|
|||
|
||||
TEST_F(saturate_propagation_test, predicated_instruction)
|
||||
{
|
||||
fs_reg dst0 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg dst1 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src0 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src1 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg dst0 = v->vgrf(glsl_float_type());
|
||||
fs_reg dst1 = v->vgrf(glsl_float_type());
|
||||
fs_reg src0 = v->vgrf(glsl_float_type());
|
||||
fs_reg src1 = v->vgrf(glsl_float_type());
|
||||
bld.ADD(dst0, src0, src1)
|
||||
->predicate = BRW_PREDICATE_NORMAL;
|
||||
set_saturate(true, bld.MOV(dst1, dst0));
|
||||
|
|
@ -225,9 +225,9 @@ TEST_F(saturate_propagation_test, predicated_instruction)
|
|||
|
||||
TEST_F(saturate_propagation_test, neg_mov_sat)
|
||||
{
|
||||
fs_reg dst0 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg dst1 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src0 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg dst0 = v->vgrf(glsl_float_type());
|
||||
fs_reg dst1 = v->vgrf(glsl_float_type());
|
||||
fs_reg src0 = v->vgrf(glsl_float_type());
|
||||
bld.RNDU(dst0, src0);
|
||||
dst0.negate = true;
|
||||
set_saturate(true, bld.MOV(dst1, dst0));
|
||||
|
|
@ -258,10 +258,10 @@ TEST_F(saturate_propagation_test, neg_mov_sat)
|
|||
|
||||
TEST_F(saturate_propagation_test, add_neg_mov_sat)
|
||||
{
|
||||
fs_reg dst0 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg dst1 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src0 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src1 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg dst0 = v->vgrf(glsl_float_type());
|
||||
fs_reg dst1 = v->vgrf(glsl_float_type());
|
||||
fs_reg src0 = v->vgrf(glsl_float_type());
|
||||
fs_reg src1 = v->vgrf(glsl_float_type());
|
||||
bld.ADD(dst0, src0, src1);
|
||||
dst0.negate = true;
|
||||
set_saturate(true, bld.MOV(dst1, dst0));
|
||||
|
|
@ -295,9 +295,9 @@ TEST_F(saturate_propagation_test, add_neg_mov_sat)
|
|||
|
||||
TEST_F(saturate_propagation_test, add_imm_float_neg_mov_sat)
|
||||
{
|
||||
fs_reg dst0 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg dst1 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src0 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg dst0 = v->vgrf(glsl_float_type());
|
||||
fs_reg dst1 = v->vgrf(glsl_float_type());
|
||||
fs_reg src0 = v->vgrf(glsl_float_type());
|
||||
fs_reg src1 = brw_imm_f(1.0f);
|
||||
bld.ADD(dst0, src0, src1);
|
||||
dst0.negate = true;
|
||||
|
|
@ -332,10 +332,10 @@ TEST_F(saturate_propagation_test, add_imm_float_neg_mov_sat)
|
|||
|
||||
TEST_F(saturate_propagation_test, mul_neg_mov_sat)
|
||||
{
|
||||
fs_reg dst0 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg dst1 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src0 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src1 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg dst0 = v->vgrf(glsl_float_type());
|
||||
fs_reg dst1 = v->vgrf(glsl_float_type());
|
||||
fs_reg src0 = v->vgrf(glsl_float_type());
|
||||
fs_reg src1 = v->vgrf(glsl_float_type());
|
||||
bld.MUL(dst0, src0, src1);
|
||||
dst0.negate = true;
|
||||
set_saturate(true, bld.MOV(dst1, dst0));
|
||||
|
|
@ -369,11 +369,11 @@ TEST_F(saturate_propagation_test, mul_neg_mov_sat)
|
|||
|
||||
TEST_F(saturate_propagation_test, mad_neg_mov_sat)
|
||||
{
|
||||
fs_reg dst0 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg dst1 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src0 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src1 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src2 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg dst0 = v->vgrf(glsl_float_type());
|
||||
fs_reg dst1 = v->vgrf(glsl_float_type());
|
||||
fs_reg src0 = v->vgrf(glsl_float_type());
|
||||
fs_reg src1 = v->vgrf(glsl_float_type());
|
||||
fs_reg src2 = v->vgrf(glsl_float_type());
|
||||
bld.MAD(dst0, src0, src1, src2);
|
||||
dst0.negate = true;
|
||||
set_saturate(true, bld.MOV(dst1, dst0));
|
||||
|
|
@ -409,11 +409,11 @@ TEST_F(saturate_propagation_test, mad_neg_mov_sat)
|
|||
|
||||
TEST_F(saturate_propagation_test, mad_imm_float_neg_mov_sat)
|
||||
{
|
||||
fs_reg dst0 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg dst1 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg dst0 = v->vgrf(glsl_float_type());
|
||||
fs_reg dst1 = v->vgrf(glsl_float_type());
|
||||
fs_reg src0 = brw_imm_f(1.0f);
|
||||
fs_reg src1 = brw_imm_f(-2.0f);
|
||||
fs_reg src2 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src2 = v->vgrf(glsl_float_type());
|
||||
/* The builder for MAD tries to be helpful and not put immediates as direct
|
||||
* sources. We want to test specifically that case.
|
||||
*/
|
||||
|
|
@ -453,11 +453,11 @@ TEST_F(saturate_propagation_test, mad_imm_float_neg_mov_sat)
|
|||
|
||||
TEST_F(saturate_propagation_test, mul_mov_sat_neg_mov_sat)
|
||||
{
|
||||
fs_reg dst0 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg dst1 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg dst2 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src0 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src1 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg dst0 = v->vgrf(glsl_float_type());
|
||||
fs_reg dst1 = v->vgrf(glsl_float_type());
|
||||
fs_reg dst2 = v->vgrf(glsl_float_type());
|
||||
fs_reg src0 = v->vgrf(glsl_float_type());
|
||||
fs_reg src1 = v->vgrf(glsl_float_type());
|
||||
bld.MUL(dst0, src0, src1);
|
||||
set_saturate(true, bld.MOV(dst1, dst0));
|
||||
dst0.negate = true;
|
||||
|
|
@ -494,11 +494,11 @@ TEST_F(saturate_propagation_test, mul_mov_sat_neg_mov_sat)
|
|||
|
||||
TEST_F(saturate_propagation_test, mul_neg_mov_sat_neg_mov_sat)
|
||||
{
|
||||
fs_reg dst0 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg dst1 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg dst2 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src0 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src1 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg dst0 = v->vgrf(glsl_float_type());
|
||||
fs_reg dst1 = v->vgrf(glsl_float_type());
|
||||
fs_reg dst2 = v->vgrf(glsl_float_type());
|
||||
fs_reg src0 = v->vgrf(glsl_float_type());
|
||||
fs_reg src1 = v->vgrf(glsl_float_type());
|
||||
bld.MUL(dst0, src0, src1);
|
||||
dst0.negate = true;
|
||||
set_saturate(true, bld.MOV(dst1, dst0));
|
||||
|
|
@ -536,10 +536,10 @@ TEST_F(saturate_propagation_test, mul_neg_mov_sat_neg_mov_sat)
|
|||
|
||||
TEST_F(saturate_propagation_test, abs_mov_sat)
|
||||
{
|
||||
fs_reg dst0 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg dst1 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src0 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src1 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg dst0 = v->vgrf(glsl_float_type());
|
||||
fs_reg dst1 = v->vgrf(glsl_float_type());
|
||||
fs_reg src0 = v->vgrf(glsl_float_type());
|
||||
fs_reg src1 = v->vgrf(glsl_float_type());
|
||||
bld.ADD(dst0, src0, src1);
|
||||
dst0.abs = true;
|
||||
set_saturate(true, bld.MOV(dst1, dst0));
|
||||
|
|
@ -570,11 +570,11 @@ TEST_F(saturate_propagation_test, abs_mov_sat)
|
|||
|
||||
TEST_F(saturate_propagation_test, producer_saturates)
|
||||
{
|
||||
fs_reg dst0 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg dst1 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg dst2 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src0 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src1 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg dst0 = v->vgrf(glsl_float_type());
|
||||
fs_reg dst1 = v->vgrf(glsl_float_type());
|
||||
fs_reg dst2 = v->vgrf(glsl_float_type());
|
||||
fs_reg src0 = v->vgrf(glsl_float_type());
|
||||
fs_reg src1 = v->vgrf(glsl_float_type());
|
||||
set_saturate(true, bld.ADD(dst0, src0, src1));
|
||||
set_saturate(true, bld.MOV(dst1, dst0));
|
||||
bld.MOV(dst2, dst0);
|
||||
|
|
@ -608,11 +608,11 @@ TEST_F(saturate_propagation_test, producer_saturates)
|
|||
|
||||
TEST_F(saturate_propagation_test, intervening_saturating_copy)
|
||||
{
|
||||
fs_reg dst0 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg dst1 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg dst2 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src0 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src1 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg dst0 = v->vgrf(glsl_float_type());
|
||||
fs_reg dst1 = v->vgrf(glsl_float_type());
|
||||
fs_reg dst2 = v->vgrf(glsl_float_type());
|
||||
fs_reg src0 = v->vgrf(glsl_float_type());
|
||||
fs_reg src1 = v->vgrf(glsl_float_type());
|
||||
bld.ADD(dst0, src0, src1);
|
||||
set_saturate(true, bld.MOV(dst1, dst0));
|
||||
set_saturate(true, bld.MOV(dst2, dst0));
|
||||
|
|
@ -648,11 +648,11 @@ TEST_F(saturate_propagation_test, intervening_saturating_copy)
|
|||
|
||||
TEST_F(saturate_propagation_test, intervening_dest_write)
|
||||
{
|
||||
fs_reg dst0 = v->vgrf(glsl_type::vec4_type);
|
||||
fs_reg dst1 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src0 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src1 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src2 = v->vgrf(glsl_type::vec2_type);
|
||||
fs_reg dst0 = v->vgrf(glsl_vec4_type());
|
||||
fs_reg dst1 = v->vgrf(glsl_float_type());
|
||||
fs_reg src0 = v->vgrf(glsl_float_type());
|
||||
fs_reg src1 = v->vgrf(glsl_float_type());
|
||||
fs_reg src2 = v->vgrf(glsl_vec2_type());
|
||||
bld.ADD(offset(dst0, bld, 2), src0, src1);
|
||||
bld.emit(SHADER_OPCODE_TEX, dst0, src2)
|
||||
->size_written = 8 * REG_SIZE;
|
||||
|
|
@ -687,11 +687,11 @@ TEST_F(saturate_propagation_test, intervening_dest_write)
|
|||
|
||||
TEST_F(saturate_propagation_test, mul_neg_mov_sat_mov_sat)
|
||||
{
|
||||
fs_reg dst0 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg dst1 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg dst2 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src0 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src1 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg dst0 = v->vgrf(glsl_float_type());
|
||||
fs_reg dst1 = v->vgrf(glsl_float_type());
|
||||
fs_reg dst2 = v->vgrf(glsl_float_type());
|
||||
fs_reg src0 = v->vgrf(glsl_float_type());
|
||||
fs_reg src1 = v->vgrf(glsl_float_type());
|
||||
bld.MUL(dst0, src0, src1);
|
||||
dst0.negate = true;
|
||||
set_saturate(true, bld.MOV(dst1, dst0));
|
||||
|
|
@ -729,10 +729,10 @@ TEST_F(saturate_propagation_test, mul_neg_mov_sat_mov_sat)
|
|||
|
||||
TEST_F(saturate_propagation_test, smaller_exec_size_consumer)
|
||||
{
|
||||
fs_reg dst0 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg dst1 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src0 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src1 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg dst0 = v->vgrf(glsl_float_type());
|
||||
fs_reg dst1 = v->vgrf(glsl_float_type());
|
||||
fs_reg src0 = v->vgrf(glsl_float_type());
|
||||
fs_reg src1 = v->vgrf(glsl_float_type());
|
||||
bld.ADD(dst0, src0, src1);
|
||||
set_saturate(true, bld.group(8, 0).MOV(dst1, dst0));
|
||||
|
||||
|
|
@ -762,10 +762,10 @@ TEST_F(saturate_propagation_test, smaller_exec_size_consumer)
|
|||
|
||||
TEST_F(saturate_propagation_test, larger_exec_size_consumer)
|
||||
{
|
||||
fs_reg dst0 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg dst1 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src0 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src1 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg dst0 = v->vgrf(glsl_float_type());
|
||||
fs_reg dst1 = v->vgrf(glsl_float_type());
|
||||
fs_reg src0 = v->vgrf(glsl_float_type());
|
||||
fs_reg src1 = v->vgrf(glsl_float_type());
|
||||
bld.group(8, 0).ADD(dst0, src0, src1);
|
||||
set_saturate(true, bld.MOV(dst1, dst0));
|
||||
|
||||
|
|
@ -795,11 +795,11 @@ TEST_F(saturate_propagation_test, larger_exec_size_consumer)
|
|||
|
||||
TEST_F(saturate_propagation_test, offset_source_barrier)
|
||||
{
|
||||
fs_reg dst0 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg dst1 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg dst2 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src0 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg src1 = v->vgrf(glsl_type::float_type);
|
||||
fs_reg dst0 = v->vgrf(glsl_float_type());
|
||||
fs_reg dst1 = v->vgrf(glsl_float_type());
|
||||
fs_reg dst2 = v->vgrf(glsl_float_type());
|
||||
fs_reg src0 = v->vgrf(glsl_float_type());
|
||||
fs_reg src1 = v->vgrf(glsl_float_type());
|
||||
bld.group(16, 0).ADD(dst0, src0, src1);
|
||||
bld.group(1, 0).ADD(dst1, component(dst0, 8), brw_imm_f(1.0f));
|
||||
set_saturate(true, bld.group(16, 0).MOV(dst2, dst0));
|
||||
|
|
|
|||
|
|
@ -150,10 +150,10 @@ TEST_F(scoreboard_test, RAW_inorder_inorder)
|
|||
{
|
||||
fs_reg g[16];
|
||||
for (unsigned i = 0; i < ARRAY_SIZE(g); i++)
|
||||
g[i] = v->vgrf(glsl_type::int_type);
|
||||
g[i] = v->vgrf(glsl_int_type());
|
||||
|
||||
fs_reg x = v->vgrf(glsl_type::int_type);
|
||||
fs_reg y = v->vgrf(glsl_type::int_type);
|
||||
fs_reg x = v->vgrf(glsl_int_type());
|
||||
fs_reg y = v->vgrf(glsl_int_type());
|
||||
bld.ADD( x, g[1], g[2]);
|
||||
bld.MUL( y, g[3], g[4]);
|
||||
bld.AND(g[5], x, y);
|
||||
|
|
@ -176,9 +176,9 @@ TEST_F(scoreboard_test, RAW_inorder_outoforder)
|
|||
{
|
||||
fs_reg g[16];
|
||||
for (unsigned i = 0; i < ARRAY_SIZE(g); i++)
|
||||
g[i] = v->vgrf(glsl_type::int_type);
|
||||
g[i] = v->vgrf(glsl_int_type());
|
||||
|
||||
fs_reg x = v->vgrf(glsl_type::int_type);
|
||||
fs_reg x = v->vgrf(glsl_int_type());
|
||||
bld.ADD( x, g[1], g[2]);
|
||||
bld.MUL( g[3], g[4], g[5]);
|
||||
emit_SEND(bld, g[6], g[7], x);
|
||||
|
|
@ -201,10 +201,10 @@ TEST_F(scoreboard_test, RAW_outoforder_inorder)
|
|||
{
|
||||
fs_reg g[16];
|
||||
for (unsigned i = 0; i < ARRAY_SIZE(g); i++)
|
||||
g[i] = v->vgrf(glsl_type::int_type);
|
||||
g[i] = v->vgrf(glsl_int_type());
|
||||
|
||||
fs_reg x = v->vgrf(glsl_type::int_type);
|
||||
fs_reg y = v->vgrf(glsl_type::int_type);
|
||||
fs_reg x = v->vgrf(glsl_int_type());
|
||||
fs_reg y = v->vgrf(glsl_int_type());
|
||||
emit_SEND(bld, x, g[1], g[2]);
|
||||
bld.MUL( y, g[3], g[4]);
|
||||
bld.AND( g[5], x, y);
|
||||
|
|
@ -227,13 +227,13 @@ TEST_F(scoreboard_test, RAW_outoforder_outoforder)
|
|||
{
|
||||
fs_reg g[16];
|
||||
for (unsigned i = 0; i < ARRAY_SIZE(g); i++)
|
||||
g[i] = v->vgrf(glsl_type::int_type);
|
||||
g[i] = v->vgrf(glsl_int_type());
|
||||
|
||||
/* The second SEND depends on the first, and would need to refer to two
|
||||
* SBIDs. Since it is not possible we expect a SYNC instruction to be
|
||||
* added.
|
||||
*/
|
||||
fs_reg x = v->vgrf(glsl_type::int_type);
|
||||
fs_reg x = v->vgrf(glsl_int_type());
|
||||
emit_SEND(bld, x, g[1], g[2]);
|
||||
emit_SEND(bld, g[3], x, g[4])->sfid++;
|
||||
|
||||
|
|
@ -259,9 +259,9 @@ TEST_F(scoreboard_test, WAR_inorder_inorder)
|
|||
{
|
||||
fs_reg g[16];
|
||||
for (unsigned i = 0; i < ARRAY_SIZE(g); i++)
|
||||
g[i] = v->vgrf(glsl_type::int_type);
|
||||
g[i] = v->vgrf(glsl_int_type());
|
||||
|
||||
fs_reg x = v->vgrf(glsl_type::int_type);
|
||||
fs_reg x = v->vgrf(glsl_int_type());
|
||||
bld.ADD(g[1], x, g[2]);
|
||||
bld.MUL(g[3], g[4], g[5]);
|
||||
bld.AND( x, g[6], g[7]);
|
||||
|
|
@ -284,9 +284,9 @@ TEST_F(scoreboard_test, WAR_inorder_outoforder)
|
|||
{
|
||||
fs_reg g[16];
|
||||
for (unsigned i = 0; i < ARRAY_SIZE(g); i++)
|
||||
g[i] = v->vgrf(glsl_type::int_type);
|
||||
g[i] = v->vgrf(glsl_int_type());
|
||||
|
||||
fs_reg x = v->vgrf(glsl_type::int_type);
|
||||
fs_reg x = v->vgrf(glsl_int_type());
|
||||
bld.ADD( g[1], x, g[2]);
|
||||
bld.MUL( g[3], g[4], g[5]);
|
||||
emit_SEND(bld, x, g[6], g[7]);
|
||||
|
|
@ -309,9 +309,9 @@ TEST_F(scoreboard_test, WAR_outoforder_inorder)
|
|||
{
|
||||
fs_reg g[16];
|
||||
for (unsigned i = 0; i < ARRAY_SIZE(g); i++)
|
||||
g[i] = v->vgrf(glsl_type::int_type);
|
||||
g[i] = v->vgrf(glsl_int_type());
|
||||
|
||||
fs_reg x = v->vgrf(glsl_type::int_type);
|
||||
fs_reg x = v->vgrf(glsl_int_type());
|
||||
emit_SEND(bld, g[1], g[2], x);
|
||||
bld.MUL( g[4], g[5], g[6]);
|
||||
bld.AND( x, g[7], g[8]);
|
||||
|
|
@ -334,9 +334,9 @@ TEST_F(scoreboard_test, WAR_outoforder_outoforder)
|
|||
{
|
||||
fs_reg g[16];
|
||||
for (unsigned i = 0; i < ARRAY_SIZE(g); i++)
|
||||
g[i] = v->vgrf(glsl_type::int_type);
|
||||
g[i] = v->vgrf(glsl_int_type());
|
||||
|
||||
fs_reg x = v->vgrf(glsl_type::int_type);
|
||||
fs_reg x = v->vgrf(glsl_int_type());
|
||||
emit_SEND(bld, g[1], g[2], x);
|
||||
emit_SEND(bld, x, g[3], g[4])->sfid++;
|
||||
|
||||
|
|
@ -362,9 +362,9 @@ TEST_F(scoreboard_test, WAW_inorder_inorder)
|
|||
{
|
||||
fs_reg g[16];
|
||||
for (unsigned i = 0; i < ARRAY_SIZE(g); i++)
|
||||
g[i] = v->vgrf(glsl_type::int_type);
|
||||
g[i] = v->vgrf(glsl_int_type());
|
||||
|
||||
fs_reg x = v->vgrf(glsl_type::int_type);
|
||||
fs_reg x = v->vgrf(glsl_int_type());
|
||||
bld.ADD( x, g[1], g[2]);
|
||||
bld.MUL(g[3], g[4], g[5]);
|
||||
bld.AND( x, g[6], g[7]);
|
||||
|
|
@ -392,9 +392,9 @@ TEST_F(scoreboard_test, WAW_inorder_outoforder)
|
|||
{
|
||||
fs_reg g[16];
|
||||
for (unsigned i = 0; i < ARRAY_SIZE(g); i++)
|
||||
g[i] = v->vgrf(glsl_type::int_type);
|
||||
g[i] = v->vgrf(glsl_int_type());
|
||||
|
||||
fs_reg x = v->vgrf(glsl_type::int_type);
|
||||
fs_reg x = v->vgrf(glsl_int_type());
|
||||
bld.ADD( x, g[1], g[2]);
|
||||
bld.MUL( g[3], g[4], g[5]);
|
||||
emit_SEND(bld, x, g[6], g[7]);
|
||||
|
|
@ -417,9 +417,9 @@ TEST_F(scoreboard_test, WAW_outoforder_inorder)
|
|||
{
|
||||
fs_reg g[16];
|
||||
for (unsigned i = 0; i < ARRAY_SIZE(g); i++)
|
||||
g[i] = v->vgrf(glsl_type::int_type);
|
||||
g[i] = v->vgrf(glsl_int_type());
|
||||
|
||||
fs_reg x = v->vgrf(glsl_type::int_type);
|
||||
fs_reg x = v->vgrf(glsl_int_type());
|
||||
emit_SEND(bld, x, g[1], g[2]);
|
||||
bld.MUL( g[3], g[4], g[5]);
|
||||
bld.AND( x, g[6], g[7]);
|
||||
|
|
@ -442,9 +442,9 @@ TEST_F(scoreboard_test, WAW_outoforder_outoforder)
|
|||
{
|
||||
fs_reg g[16];
|
||||
for (unsigned i = 0; i < ARRAY_SIZE(g); i++)
|
||||
g[i] = v->vgrf(glsl_type::int_type);
|
||||
g[i] = v->vgrf(glsl_int_type());
|
||||
|
||||
fs_reg x = v->vgrf(glsl_type::int_type);
|
||||
fs_reg x = v->vgrf(glsl_int_type());
|
||||
emit_SEND(bld, x, g[1], g[2]);
|
||||
emit_SEND(bld, x, g[3], g[4])->sfid++;
|
||||
|
||||
|
|
@ -471,9 +471,9 @@ TEST_F(scoreboard_test, loop1)
|
|||
{
|
||||
fs_reg g[16];
|
||||
for (unsigned i = 0; i < ARRAY_SIZE(g); i++)
|
||||
g[i] = v->vgrf(glsl_type::int_type);
|
||||
g[i] = v->vgrf(glsl_int_type());
|
||||
|
||||
fs_reg x = v->vgrf(glsl_type::int_type);
|
||||
fs_reg x = v->vgrf(glsl_int_type());
|
||||
bld.XOR( x, g[1], g[2]);
|
||||
|
||||
bld.emit(BRW_OPCODE_DO);
|
||||
|
|
@ -501,9 +501,9 @@ TEST_F(scoreboard_test, loop2)
|
|||
{
|
||||
fs_reg g[16];
|
||||
for (unsigned i = 0; i < ARRAY_SIZE(g); i++)
|
||||
g[i] = v->vgrf(glsl_type::int_type);
|
||||
g[i] = v->vgrf(glsl_int_type());
|
||||
|
||||
fs_reg x = v->vgrf(glsl_type::int_type);
|
||||
fs_reg x = v->vgrf(glsl_int_type());
|
||||
bld.XOR( x, g[1], g[2]);
|
||||
bld.XOR(g[3], g[1], g[2]);
|
||||
bld.XOR(g[4], g[1], g[2]);
|
||||
|
|
@ -536,9 +536,9 @@ TEST_F(scoreboard_test, loop3)
|
|||
{
|
||||
fs_reg g[16];
|
||||
for (unsigned i = 0; i < ARRAY_SIZE(g); i++)
|
||||
g[i] = v->vgrf(glsl_type::int_type);
|
||||
g[i] = v->vgrf(glsl_int_type());
|
||||
|
||||
fs_reg x = v->vgrf(glsl_type::int_type);
|
||||
fs_reg x = v->vgrf(glsl_int_type());
|
||||
bld.XOR( x, g[1], g[2]);
|
||||
|
||||
bld.emit(BRW_OPCODE_DO);
|
||||
|
|
@ -573,9 +573,9 @@ TEST_F(scoreboard_test, conditional1)
|
|||
{
|
||||
fs_reg g[16];
|
||||
for (unsigned i = 0; i < ARRAY_SIZE(g); i++)
|
||||
g[i] = v->vgrf(glsl_type::int_type);
|
||||
g[i] = v->vgrf(glsl_int_type());
|
||||
|
||||
fs_reg x = v->vgrf(glsl_type::int_type);
|
||||
fs_reg x = v->vgrf(glsl_int_type());
|
||||
bld.XOR( x, g[1], g[2]);
|
||||
bld.emit(BRW_OPCODE_IF);
|
||||
|
||||
|
|
@ -602,9 +602,9 @@ TEST_F(scoreboard_test, conditional2)
|
|||
{
|
||||
fs_reg g[16];
|
||||
for (unsigned i = 0; i < ARRAY_SIZE(g); i++)
|
||||
g[i] = v->vgrf(glsl_type::int_type);
|
||||
g[i] = v->vgrf(glsl_int_type());
|
||||
|
||||
fs_reg x = v->vgrf(glsl_type::int_type);
|
||||
fs_reg x = v->vgrf(glsl_int_type());
|
||||
bld.XOR( x, g[1], g[2]);
|
||||
bld.XOR(g[3], g[1], g[2]);
|
||||
bld.XOR(g[4], g[1], g[2]);
|
||||
|
|
@ -634,9 +634,9 @@ TEST_F(scoreboard_test, conditional3)
|
|||
{
|
||||
fs_reg g[16];
|
||||
for (unsigned i = 0; i < ARRAY_SIZE(g); i++)
|
||||
g[i] = v->vgrf(glsl_type::int_type);
|
||||
g[i] = v->vgrf(glsl_int_type());
|
||||
|
||||
fs_reg x = v->vgrf(glsl_type::int_type);
|
||||
fs_reg x = v->vgrf(glsl_int_type());
|
||||
bld.XOR( x, g[1], g[2]);
|
||||
bld.emit(BRW_OPCODE_IF);
|
||||
|
||||
|
|
@ -666,9 +666,9 @@ TEST_F(scoreboard_test, conditional4)
|
|||
{
|
||||
fs_reg g[16];
|
||||
for (unsigned i = 0; i < ARRAY_SIZE(g); i++)
|
||||
g[i] = v->vgrf(glsl_type::int_type);
|
||||
g[i] = v->vgrf(glsl_int_type());
|
||||
|
||||
fs_reg x = v->vgrf(glsl_type::int_type);
|
||||
fs_reg x = v->vgrf(glsl_int_type());
|
||||
bld.XOR( x, g[1], g[2]);
|
||||
bld.emit(BRW_OPCODE_IF);
|
||||
|
||||
|
|
@ -698,9 +698,9 @@ TEST_F(scoreboard_test, conditional5)
|
|||
{
|
||||
fs_reg g[16];
|
||||
for (unsigned i = 0; i < ARRAY_SIZE(g); i++)
|
||||
g[i] = v->vgrf(glsl_type::int_type);
|
||||
g[i] = v->vgrf(glsl_int_type());
|
||||
|
||||
fs_reg x = v->vgrf(glsl_type::int_type);
|
||||
fs_reg x = v->vgrf(glsl_int_type());
|
||||
bld.XOR( x, g[1], g[2]);
|
||||
bld.emit(BRW_OPCODE_IF);
|
||||
|
||||
|
|
@ -735,9 +735,9 @@ TEST_F(scoreboard_test, conditional6)
|
|||
{
|
||||
fs_reg g[16];
|
||||
for (unsigned i = 0; i < ARRAY_SIZE(g); i++)
|
||||
g[i] = v->vgrf(glsl_type::int_type);
|
||||
g[i] = v->vgrf(glsl_int_type());
|
||||
|
||||
fs_reg x = v->vgrf(glsl_type::int_type);
|
||||
fs_reg x = v->vgrf(glsl_int_type());
|
||||
bld.XOR( x, g[1], g[2]);
|
||||
bld.emit(BRW_OPCODE_IF);
|
||||
|
||||
|
|
@ -779,9 +779,9 @@ TEST_F(scoreboard_test, conditional7)
|
|||
{
|
||||
fs_reg g[16];
|
||||
for (unsigned i = 0; i < ARRAY_SIZE(g); i++)
|
||||
g[i] = v->vgrf(glsl_type::int_type);
|
||||
g[i] = v->vgrf(glsl_int_type());
|
||||
|
||||
fs_reg x = v->vgrf(glsl_type::int_type);
|
||||
fs_reg x = v->vgrf(glsl_int_type());
|
||||
bld.XOR( x, g[1], g[2]);
|
||||
bld.emit(BRW_OPCODE_IF);
|
||||
|
||||
|
|
@ -823,9 +823,9 @@ TEST_F(scoreboard_test, conditional8)
|
|||
{
|
||||
fs_reg g[16];
|
||||
for (unsigned i = 0; i < ARRAY_SIZE(g); i++)
|
||||
g[i] = v->vgrf(glsl_type::int_type);
|
||||
g[i] = v->vgrf(glsl_int_type());
|
||||
|
||||
fs_reg x = v->vgrf(glsl_type::int_type);
|
||||
fs_reg x = v->vgrf(glsl_int_type());
|
||||
bld.XOR( x, g[1], g[2]);
|
||||
bld.XOR(g[3], g[1], g[2]);
|
||||
bld.XOR(g[4], g[1], g[2]);
|
||||
|
|
@ -869,10 +869,10 @@ TEST_F(scoreboard_test, gfx125_RaR_over_different_pipes)
|
|||
devinfo->verx10 = 125;
|
||||
brw_init_isa_info(&compiler->isa, devinfo);
|
||||
|
||||
fs_reg a = v->vgrf(glsl_type::int_type);
|
||||
fs_reg b = v->vgrf(glsl_type::int_type);
|
||||
fs_reg f = v->vgrf(glsl_type::float_type);
|
||||
fs_reg x = v->vgrf(glsl_type::int_type);
|
||||
fs_reg a = v->vgrf(glsl_int_type());
|
||||
fs_reg b = v->vgrf(glsl_int_type());
|
||||
fs_reg f = v->vgrf(glsl_float_type());
|
||||
fs_reg x = v->vgrf(glsl_int_type());
|
||||
|
||||
bld.ADD(f, x, x);
|
||||
bld.ADD(a, x, x);
|
||||
|
|
|
|||
|
|
@ -158,9 +158,9 @@ cmod_propagation(vec4_visitor *v)
|
|||
TEST_F(cmod_propagation_vec4_test, basic)
|
||||
{
|
||||
const vec4_builder bld = vec4_builder(v).at_end();
|
||||
dst_reg dest = dst_reg(v, glsl_type::float_type);
|
||||
src_reg src0 = src_reg(v, glsl_type::float_type);
|
||||
src_reg src1 = src_reg(v, glsl_type::float_type);
|
||||
dst_reg dest = dst_reg(v, glsl_float_type());
|
||||
src_reg src0 = src_reg(v, glsl_float_type());
|
||||
src_reg src1 = src_reg(v, glsl_float_type());
|
||||
src_reg zero(brw_imm_f(0.0f));
|
||||
dst_reg dest_null = bld.null_reg_f();
|
||||
dest_null.writemask = WRITEMASK_X;
|
||||
|
|
@ -194,9 +194,9 @@ TEST_F(cmod_propagation_vec4_test, basic)
|
|||
TEST_F(cmod_propagation_vec4_test, basic_different_dst_writemask)
|
||||
{
|
||||
const vec4_builder bld = vec4_builder(v).at_end();
|
||||
dst_reg dest = dst_reg(v, glsl_type::float_type);
|
||||
src_reg src0 = src_reg(v, glsl_type::float_type);
|
||||
src_reg src1 = src_reg(v, glsl_type::float_type);
|
||||
dst_reg dest = dst_reg(v, glsl_float_type());
|
||||
src_reg src0 = src_reg(v, glsl_float_type());
|
||||
src_reg src1 = src_reg(v, glsl_float_type());
|
||||
src_reg zero(brw_imm_f(0.0f));
|
||||
dst_reg dest_null = bld.null_reg_f();
|
||||
|
||||
|
|
@ -231,8 +231,8 @@ TEST_F(cmod_propagation_vec4_test, basic_different_dst_writemask)
|
|||
TEST_F(cmod_propagation_vec4_test, andz_one)
|
||||
{
|
||||
const vec4_builder bld = vec4_builder(v).at_end();
|
||||
dst_reg dest = dst_reg(v, glsl_type::int_type);
|
||||
src_reg src0 = src_reg(v, glsl_type::float_type);
|
||||
dst_reg dest = dst_reg(v, glsl_int_type());
|
||||
src_reg src0 = src_reg(v, glsl_float_type());
|
||||
src_reg zero(brw_imm_f(0.0f));
|
||||
src_reg one(brw_imm_d(1));
|
||||
|
||||
|
|
@ -267,8 +267,8 @@ TEST_F(cmod_propagation_vec4_test, andz_one)
|
|||
TEST_F(cmod_propagation_vec4_test, non_cmod_instruction)
|
||||
{
|
||||
const vec4_builder bld = vec4_builder(v).at_end();
|
||||
dst_reg dest = dst_reg(v, glsl_type::uint_type);
|
||||
src_reg src0 = src_reg(v, glsl_type::uint_type);
|
||||
dst_reg dest = dst_reg(v, glsl_uint_type());
|
||||
src_reg src0 = src_reg(v, glsl_uint_type());
|
||||
src_reg zero(brw_imm_ud(0u));
|
||||
bld.FBL(dest, src0);
|
||||
bld.CMP(bld.null_reg_ud(), src_reg(dest), zero, BRW_CONDITIONAL_GE);
|
||||
|
|
@ -300,10 +300,10 @@ TEST_F(cmod_propagation_vec4_test, non_cmod_instruction)
|
|||
TEST_F(cmod_propagation_vec4_test, intervening_flag_write)
|
||||
{
|
||||
const vec4_builder bld = vec4_builder(v).at_end();
|
||||
dst_reg dest = dst_reg(v, glsl_type::float_type);
|
||||
src_reg src0 = src_reg(v, glsl_type::float_type);
|
||||
src_reg src1 = src_reg(v, glsl_type::float_type);
|
||||
src_reg src2 = src_reg(v, glsl_type::float_type);
|
||||
dst_reg dest = dst_reg(v, glsl_float_type());
|
||||
src_reg src0 = src_reg(v, glsl_float_type());
|
||||
src_reg src1 = src_reg(v, glsl_float_type());
|
||||
src_reg src2 = src_reg(v, glsl_float_type());
|
||||
src_reg zero(brw_imm_f(0.0f));
|
||||
bld.ADD(dest, src0, src1);
|
||||
bld.CMP(bld.null_reg_f(), src2, zero, BRW_CONDITIONAL_GE);
|
||||
|
|
@ -339,11 +339,11 @@ TEST_F(cmod_propagation_vec4_test, intervening_flag_write)
|
|||
TEST_F(cmod_propagation_vec4_test, intervening_flag_read)
|
||||
{
|
||||
const vec4_builder bld = vec4_builder(v).at_end();
|
||||
dst_reg dest0 = dst_reg(v, glsl_type::float_type);
|
||||
dst_reg dest1 = dst_reg(v, glsl_type::float_type);
|
||||
src_reg src0 = src_reg(v, glsl_type::float_type);
|
||||
src_reg src1 = src_reg(v, glsl_type::float_type);
|
||||
src_reg src2 = src_reg(v, glsl_type::float_type);
|
||||
dst_reg dest0 = dst_reg(v, glsl_float_type());
|
||||
dst_reg dest1 = dst_reg(v, glsl_float_type());
|
||||
src_reg src0 = src_reg(v, glsl_float_type());
|
||||
src_reg src1 = src_reg(v, glsl_float_type());
|
||||
src_reg src2 = src_reg(v, glsl_float_type());
|
||||
src_reg zero(brw_imm_f(0.0f));
|
||||
bld.ADD(dest0, src0, src1);
|
||||
set_predicate(BRW_PREDICATE_NORMAL, bld.SEL(dest1, src2, zero));
|
||||
|
|
@ -379,10 +379,10 @@ TEST_F(cmod_propagation_vec4_test, intervening_flag_read)
|
|||
TEST_F(cmod_propagation_vec4_test, intervening_dest_write)
|
||||
{
|
||||
const vec4_builder bld = vec4_builder(v).at_end();
|
||||
dst_reg dest = dst_reg(v, glsl_type::vec4_type);
|
||||
src_reg src0 = src_reg(v, glsl_type::float_type);
|
||||
src_reg src1 = src_reg(v, glsl_type::float_type);
|
||||
src_reg src2 = src_reg(v, glsl_type::vec2_type);
|
||||
dst_reg dest = dst_reg(v, glsl_vec4_type());
|
||||
src_reg src0 = src_reg(v, glsl_float_type());
|
||||
src_reg src1 = src_reg(v, glsl_float_type());
|
||||
src_reg src2 = src_reg(v, glsl_vec2_type());
|
||||
src_reg zero(brw_imm_f(0.0f));
|
||||
bld.ADD(offset(dest, 8, 2), src0, src1);
|
||||
bld.emit(SHADER_OPCODE_TEX, dest, src2)
|
||||
|
|
@ -420,11 +420,11 @@ TEST_F(cmod_propagation_vec4_test, intervening_dest_write)
|
|||
TEST_F(cmod_propagation_vec4_test, intervening_flag_read_same_value)
|
||||
{
|
||||
const vec4_builder bld = vec4_builder(v).at_end();
|
||||
dst_reg dest0 = dst_reg(v, glsl_type::float_type);
|
||||
dst_reg dest1 = dst_reg(v, glsl_type::float_type);
|
||||
src_reg src0 = src_reg(v, glsl_type::float_type);
|
||||
src_reg src1 = src_reg(v, glsl_type::float_type);
|
||||
src_reg src2 = src_reg(v, glsl_type::float_type);
|
||||
dst_reg dest0 = dst_reg(v, glsl_float_type());
|
||||
dst_reg dest1 = dst_reg(v, glsl_float_type());
|
||||
src_reg src0 = src_reg(v, glsl_float_type());
|
||||
src_reg src1 = src_reg(v, glsl_float_type());
|
||||
src_reg src2 = src_reg(v, glsl_float_type());
|
||||
src_reg zero(brw_imm_f(0.0f));
|
||||
dst_reg dest_null = bld.null_reg_f();
|
||||
dest_null.writemask = WRITEMASK_X;
|
||||
|
|
@ -462,9 +462,9 @@ TEST_F(cmod_propagation_vec4_test, intervening_flag_read_same_value)
|
|||
TEST_F(cmod_propagation_vec4_test, negate)
|
||||
{
|
||||
const vec4_builder bld = vec4_builder(v).at_end();
|
||||
dst_reg dest = dst_reg(v, glsl_type::float_type);
|
||||
src_reg src0 = src_reg(v, glsl_type::float_type);
|
||||
src_reg src1 = src_reg(v, glsl_type::float_type);
|
||||
dst_reg dest = dst_reg(v, glsl_float_type());
|
||||
src_reg src0 = src_reg(v, glsl_float_type());
|
||||
src_reg src1 = src_reg(v, glsl_float_type());
|
||||
src_reg zero(brw_imm_f(0.0f));
|
||||
bld.ADD(dest, src0, src1);
|
||||
src_reg tmp_src = src_reg(dest);
|
||||
|
|
@ -498,9 +498,9 @@ TEST_F(cmod_propagation_vec4_test, negate)
|
|||
TEST_F(cmod_propagation_vec4_test, movnz)
|
||||
{
|
||||
const vec4_builder bld = vec4_builder(v).at_end();
|
||||
dst_reg dest = dst_reg(v, glsl_type::float_type);
|
||||
src_reg src0 = src_reg(v, glsl_type::float_type);
|
||||
src_reg src1 = src_reg(v, glsl_type::float_type);
|
||||
dst_reg dest = dst_reg(v, glsl_float_type());
|
||||
src_reg src0 = src_reg(v, glsl_float_type());
|
||||
src_reg src1 = src_reg(v, glsl_float_type());
|
||||
dst_reg dest_null = bld.null_reg_f();
|
||||
dest_null.writemask = WRITEMASK_X;
|
||||
|
||||
|
|
@ -534,9 +534,9 @@ TEST_F(cmod_propagation_vec4_test, movnz)
|
|||
TEST_F(cmod_propagation_vec4_test, different_types_cmod_with_zero)
|
||||
{
|
||||
const vec4_builder bld = vec4_builder(v).at_end();
|
||||
dst_reg dest = dst_reg(v, glsl_type::int_type);
|
||||
src_reg src0 = src_reg(v, glsl_type::int_type);
|
||||
src_reg src1 = src_reg(v, glsl_type::int_type);
|
||||
dst_reg dest = dst_reg(v, glsl_int_type());
|
||||
src_reg src0 = src_reg(v, glsl_int_type());
|
||||
src_reg src1 = src_reg(v, glsl_int_type());
|
||||
src_reg zero(brw_imm_f(0.0f));
|
||||
bld.ADD(dest, src0, src1);
|
||||
bld.CMP(bld.null_reg_f(), retype(src_reg(dest), BRW_REGISTER_TYPE_F), zero,
|
||||
|
|
@ -569,8 +569,8 @@ TEST_F(cmod_propagation_vec4_test, different_types_cmod_with_zero)
|
|||
TEST_F(cmod_propagation_vec4_test, andnz_non_one)
|
||||
{
|
||||
const vec4_builder bld = vec4_builder(v).at_end();
|
||||
dst_reg dest = dst_reg(v, glsl_type::int_type);
|
||||
src_reg src0 = src_reg(v, glsl_type::float_type);
|
||||
dst_reg dest = dst_reg(v, glsl_int_type());
|
||||
src_reg src0 = src_reg(v, glsl_float_type());
|
||||
src_reg zero(brw_imm_f(0.0f));
|
||||
src_reg nonone(brw_imm_d(38));
|
||||
|
||||
|
|
@ -607,9 +607,9 @@ TEST_F(cmod_propagation_vec4_test, andnz_non_one)
|
|||
TEST_F(cmod_propagation_vec4_test, basic_vec4)
|
||||
{
|
||||
const vec4_builder bld = vec4_builder(v).at_end();
|
||||
dst_reg dest = dst_reg(v, glsl_type::vec4_type);
|
||||
src_reg src0 = src_reg(v, glsl_type::vec4_type);
|
||||
src_reg src1 = src_reg(v, glsl_type::vec4_type);
|
||||
dst_reg dest = dst_reg(v, glsl_vec4_type());
|
||||
src_reg src0 = src_reg(v, glsl_vec4_type());
|
||||
src_reg src1 = src_reg(v, glsl_vec4_type());
|
||||
src_reg zero(brw_imm_f(0.0f));
|
||||
|
||||
bld.MUL(dest, src0, src1);
|
||||
|
|
@ -640,10 +640,10 @@ TEST_F(cmod_propagation_vec4_test, basic_vec4)
|
|||
TEST_F(cmod_propagation_vec4_test, basic_vec4_different_dst_writemask)
|
||||
{
|
||||
const vec4_builder bld = vec4_builder(v).at_end();
|
||||
dst_reg dest = dst_reg(v, glsl_type::vec4_type);
|
||||
dst_reg dest = dst_reg(v, glsl_vec4_type());
|
||||
dest.writemask = WRITEMASK_X;
|
||||
src_reg src0 = src_reg(v, glsl_type::vec4_type);
|
||||
src_reg src1 = src_reg(v, glsl_type::vec4_type);
|
||||
src_reg src0 = src_reg(v, glsl_vec4_type());
|
||||
src_reg src1 = src_reg(v, glsl_vec4_type());
|
||||
src_reg zero(brw_imm_f(0.0f));
|
||||
dst_reg dest_null = bld.null_reg_f();
|
||||
|
||||
|
|
@ -677,11 +677,11 @@ TEST_F(cmod_propagation_vec4_test, basic_vec4_different_dst_writemask)
|
|||
TEST_F(cmod_propagation_vec4_test, mad_one_component_vec4)
|
||||
{
|
||||
const vec4_builder bld = vec4_builder(v).at_end();
|
||||
dst_reg dest = dst_reg(v, glsl_type::vec4_type);
|
||||
dst_reg dest = dst_reg(v, glsl_vec4_type());
|
||||
dest.writemask = WRITEMASK_X;
|
||||
src_reg src0 = src_reg(v, glsl_type::vec4_type);
|
||||
src_reg src1 = src_reg(v, glsl_type::vec4_type);
|
||||
src_reg src2 = src_reg(v, glsl_type::vec4_type);
|
||||
src_reg src0 = src_reg(v, glsl_vec4_type());
|
||||
src_reg src1 = src_reg(v, glsl_vec4_type());
|
||||
src_reg src2 = src_reg(v, glsl_vec4_type());
|
||||
src0.swizzle = src1.swizzle = src2.swizzle = BRW_SWIZZLE_XXXX;
|
||||
src2.negate = true;
|
||||
src_reg zero(brw_imm_f(0.0f));
|
||||
|
|
@ -719,11 +719,11 @@ TEST_F(cmod_propagation_vec4_test, mad_one_component_vec4)
|
|||
TEST_F(cmod_propagation_vec4_test, mad_more_one_component_vec4)
|
||||
{
|
||||
const vec4_builder bld = vec4_builder(v).at_end();
|
||||
dst_reg dest = dst_reg(v, glsl_type::vec4_type);
|
||||
dst_reg dest = dst_reg(v, glsl_vec4_type());
|
||||
dest.writemask = WRITEMASK_XW;
|
||||
src_reg src0 = src_reg(v, glsl_type::vec4_type);
|
||||
src_reg src1 = src_reg(v, glsl_type::vec4_type);
|
||||
src_reg src2 = src_reg(v, glsl_type::vec4_type);
|
||||
src_reg src0 = src_reg(v, glsl_vec4_type());
|
||||
src_reg src1 = src_reg(v, glsl_vec4_type());
|
||||
src_reg src2 = src_reg(v, glsl_vec4_type());
|
||||
src0.swizzle = src1.swizzle = src2.swizzle = BRW_SWIZZLE_XXXX;
|
||||
src2.negate = true;
|
||||
src_reg zero(brw_imm_f(0.0f));
|
||||
|
|
@ -762,9 +762,9 @@ TEST_F(cmod_propagation_vec4_test, mad_more_one_component_vec4)
|
|||
TEST_F(cmod_propagation_vec4_test, cmp_mov_vec4)
|
||||
{
|
||||
const vec4_builder bld = vec4_builder(v).at_end();
|
||||
dst_reg dest = dst_reg(v, glsl_type::ivec4_type);
|
||||
dst_reg dest = dst_reg(v, glsl_ivec4_type());
|
||||
dest.writemask = WRITEMASK_X;
|
||||
src_reg src0 = src_reg(v, glsl_type::ivec4_type);
|
||||
src_reg src0 = src_reg(v, glsl_ivec4_type());
|
||||
src0.swizzle = BRW_SWIZZLE_XXXX;
|
||||
src0.file = UNIFORM;
|
||||
src_reg nonone = retype(brw_imm_d(16), BRW_REGISTER_TYPE_D);
|
||||
|
|
@ -803,9 +803,9 @@ TEST_F(cmod_propagation_vec4_test, cmp_mov_vec4)
|
|||
TEST_F(cmod_propagation_vec4_test, mul_cmp_different_channels_vec4)
|
||||
{
|
||||
const vec4_builder bld = vec4_builder(v).at_end();
|
||||
dst_reg dest = dst_reg(v, glsl_type::vec4_type);
|
||||
src_reg src0 = src_reg(v, glsl_type::vec4_type);
|
||||
src_reg src1 = src_reg(v, glsl_type::vec4_type);
|
||||
dst_reg dest = dst_reg(v, glsl_vec4_type());
|
||||
src_reg src0 = src_reg(v, glsl_vec4_type());
|
||||
src_reg src1 = src_reg(v, glsl_vec4_type());
|
||||
src_reg zero(brw_imm_f(0.0f));
|
||||
src_reg cmp_src = src_reg(dest);
|
||||
cmp_src.swizzle = BRW_SWIZZLE4(0,1,3,2);
|
||||
|
|
@ -840,9 +840,9 @@ TEST_F(cmod_propagation_vec4_test, mul_cmp_different_channels_vec4)
|
|||
TEST_F(cmod_propagation_vec4_test, add_cmp_same_dst_writemask)
|
||||
{
|
||||
const vec4_builder bld = vec4_builder(v).at_end();
|
||||
dst_reg dest = dst_reg(v, glsl_type::vec4_type);
|
||||
src_reg src0 = src_reg(v, glsl_type::vec4_type);
|
||||
src_reg src1 = src_reg(v, glsl_type::vec4_type);
|
||||
dst_reg dest = dst_reg(v, glsl_vec4_type());
|
||||
src_reg src0 = src_reg(v, glsl_vec4_type());
|
||||
src_reg src1 = src_reg(v, glsl_vec4_type());
|
||||
dst_reg dest_null = bld.null_reg_f();
|
||||
|
||||
bld.ADD(dest, src0, src1);
|
||||
|
|
@ -875,9 +875,9 @@ TEST_F(cmod_propagation_vec4_test, add_cmp_same_dst_writemask)
|
|||
TEST_F(cmod_propagation_vec4_test, add_cmp_different_dst_writemask)
|
||||
{
|
||||
const vec4_builder bld = vec4_builder(v).at_end();
|
||||
dst_reg dest = dst_reg(v, glsl_type::float_type);
|
||||
src_reg src0 = src_reg(v, glsl_type::vec4_type);
|
||||
src_reg src1 = src_reg(v, glsl_type::vec4_type);
|
||||
dst_reg dest = dst_reg(v, glsl_float_type());
|
||||
src_reg src0 = src_reg(v, glsl_vec4_type());
|
||||
src_reg src1 = src_reg(v, glsl_vec4_type());
|
||||
dst_reg dest_null = bld.null_reg_f();
|
||||
|
||||
bld.ADD(dest, src0, src1);
|
||||
|
|
@ -912,12 +912,12 @@ TEST_F(cmod_propagation_vec4_test, add_cmp_different_dst_writemask)
|
|||
TEST_F(cmod_propagation_vec4_test, prop_across_sel_gfx7)
|
||||
{
|
||||
const vec4_builder bld = vec4_builder(v).at_end();
|
||||
dst_reg dest1 = dst_reg(v, glsl_type::float_type);
|
||||
dst_reg dest2 = dst_reg(v, glsl_type::float_type);
|
||||
src_reg src0 = src_reg(v, glsl_type::float_type);
|
||||
src_reg src1 = src_reg(v, glsl_type::float_type);
|
||||
src_reg src2 = src_reg(v, glsl_type::float_type);
|
||||
src_reg src3 = src_reg(v, glsl_type::float_type);
|
||||
dst_reg dest1 = dst_reg(v, glsl_float_type());
|
||||
dst_reg dest2 = dst_reg(v, glsl_float_type());
|
||||
src_reg src0 = src_reg(v, glsl_float_type());
|
||||
src_reg src1 = src_reg(v, glsl_float_type());
|
||||
src_reg src2 = src_reg(v, glsl_float_type());
|
||||
src_reg src3 = src_reg(v, glsl_float_type());
|
||||
src_reg zero(brw_imm_f(0.0f));
|
||||
dst_reg dest_null = bld.null_reg_f();
|
||||
dest_null.writemask = WRITEMASK_X;
|
||||
|
|
@ -960,12 +960,12 @@ TEST_F(cmod_propagation_vec4_test, prop_across_sel_gfx5)
|
|||
devinfo->verx10 = devinfo->ver * 10;
|
||||
|
||||
const vec4_builder bld = vec4_builder(v).at_end();
|
||||
dst_reg dest1 = dst_reg(v, glsl_type::float_type);
|
||||
dst_reg dest2 = dst_reg(v, glsl_type::float_type);
|
||||
src_reg src0 = src_reg(v, glsl_type::float_type);
|
||||
src_reg src1 = src_reg(v, glsl_type::float_type);
|
||||
src_reg src2 = src_reg(v, glsl_type::float_type);
|
||||
src_reg src3 = src_reg(v, glsl_type::float_type);
|
||||
dst_reg dest1 = dst_reg(v, glsl_float_type());
|
||||
dst_reg dest2 = dst_reg(v, glsl_float_type());
|
||||
src_reg src0 = src_reg(v, glsl_float_type());
|
||||
src_reg src1 = src_reg(v, glsl_float_type());
|
||||
src_reg src2 = src_reg(v, glsl_float_type());
|
||||
src_reg src3 = src_reg(v, glsl_float_type());
|
||||
src_reg zero(brw_imm_f(0.0f));
|
||||
dst_reg dest_null = bld.null_reg_f();
|
||||
dest_null.writemask = WRITEMASK_X;
|
||||
|
|
@ -1014,9 +1014,9 @@ TEST_F(cmod_propagation_vec4_test, prop_into_sel_gfx5)
|
|||
devinfo->verx10 = devinfo->ver * 10;
|
||||
|
||||
const vec4_builder bld = vec4_builder(v).at_end();
|
||||
dst_reg dest = dst_reg(v, glsl_type::float_type);
|
||||
src_reg src0 = src_reg(v, glsl_type::float_type);
|
||||
src_reg src1 = src_reg(v, glsl_type::float_type);
|
||||
dst_reg dest = dst_reg(v, glsl_float_type());
|
||||
src_reg src0 = src_reg(v, glsl_float_type());
|
||||
src_reg src1 = src_reg(v, glsl_float_type());
|
||||
src_reg zero(brw_imm_f(0.0f));
|
||||
dst_reg dest_null = bld.null_reg_f();
|
||||
dest_null.writemask = WRITEMASK_X;
|
||||
|
|
|
|||
|
|
@ -137,9 +137,9 @@ copy_propagation(vec4_visitor *v)
|
|||
|
||||
TEST_F(copy_propagation_vec4_test, test_swizzle_swizzle)
|
||||
{
|
||||
dst_reg a = dst_reg(v, glsl_type::vec4_type);
|
||||
dst_reg b = dst_reg(v, glsl_type::vec4_type);
|
||||
dst_reg c = dst_reg(v, glsl_type::vec4_type);
|
||||
dst_reg a = dst_reg(v, glsl_vec4_type());
|
||||
dst_reg b = dst_reg(v, glsl_vec4_type());
|
||||
dst_reg c = dst_reg(v, glsl_vec4_type());
|
||||
|
||||
v->emit(v->ADD(a, src_reg(a), src_reg(a)));
|
||||
|
||||
|
|
@ -166,9 +166,9 @@ TEST_F(copy_propagation_vec4_test, test_swizzle_swizzle)
|
|||
|
||||
TEST_F(copy_propagation_vec4_test, test_swizzle_writemask)
|
||||
{
|
||||
dst_reg a = dst_reg(v, glsl_type::vec4_type);
|
||||
dst_reg b = dst_reg(v, glsl_type::vec4_type);
|
||||
dst_reg c = dst_reg(v, glsl_type::vec4_type);
|
||||
dst_reg a = dst_reg(v, glsl_vec4_type());
|
||||
dst_reg b = dst_reg(v, glsl_vec4_type());
|
||||
dst_reg c = dst_reg(v, glsl_vec4_type());
|
||||
|
||||
v->emit(v->MOV(b, swizzle(src_reg(a), BRW_SWIZZLE4(BRW_SWIZZLE_X,
|
||||
BRW_SWIZZLE_Y,
|
||||
|
|
|
|||
|
|
@ -137,12 +137,12 @@ dead_code_eliminate(vec4_visitor *v)
|
|||
TEST_F(dead_code_eliminate_vec4_test, some_dead_channels_all_flags_used)
|
||||
{
|
||||
const vec4_builder bld = vec4_builder(v).at_end();
|
||||
src_reg r1 = src_reg(v, glsl_type::vec4_type);
|
||||
src_reg r2 = src_reg(v, glsl_type::vec4_type);
|
||||
src_reg r3 = src_reg(v, glsl_type::vec4_type);
|
||||
src_reg r4 = src_reg(v, glsl_type::vec4_type);
|
||||
src_reg r5 = src_reg(v, glsl_type::vec4_type);
|
||||
src_reg r6 = src_reg(v, glsl_type::vec4_type);
|
||||
src_reg r1 = src_reg(v, glsl_vec4_type());
|
||||
src_reg r2 = src_reg(v, glsl_vec4_type());
|
||||
src_reg r3 = src_reg(v, glsl_vec4_type());
|
||||
src_reg r4 = src_reg(v, glsl_vec4_type());
|
||||
src_reg r5 = src_reg(v, glsl_vec4_type());
|
||||
src_reg r6 = src_reg(v, glsl_vec4_type());
|
||||
|
||||
/* Sequence like the following should not be modified by DCE.
|
||||
*
|
||||
|
|
|
|||
|
|
@ -140,8 +140,8 @@ _register_coalesce(vec4_visitor *v, const char *func)
|
|||
|
||||
TEST_F(register_coalesce_vec4_test, test_compute_to_mrf)
|
||||
{
|
||||
src_reg something = src_reg(v, glsl_type::float_type);
|
||||
dst_reg temp = dst_reg(v, glsl_type::float_type);
|
||||
src_reg something = src_reg(v, glsl_float_type());
|
||||
dst_reg temp = dst_reg(v, glsl_float_type());
|
||||
dst_reg init;
|
||||
|
||||
dst_reg m0 = dst_reg(MRF, 0);
|
||||
|
|
@ -159,8 +159,8 @@ TEST_F(register_coalesce_vec4_test, test_compute_to_mrf)
|
|||
|
||||
TEST_F(register_coalesce_vec4_test, test_multiple_use)
|
||||
{
|
||||
src_reg something = src_reg(v, glsl_type::float_type);
|
||||
dst_reg temp = dst_reg(v, glsl_type::vec4_type);
|
||||
src_reg something = src_reg(v, glsl_float_type());
|
||||
dst_reg temp = dst_reg(v, glsl_vec4_type());
|
||||
dst_reg init;
|
||||
|
||||
dst_reg m0 = dst_reg(MRF, 0);
|
||||
|
|
@ -185,15 +185,15 @@ TEST_F(register_coalesce_vec4_test, test_multiple_use)
|
|||
|
||||
TEST_F(register_coalesce_vec4_test, test_dp4_mrf)
|
||||
{
|
||||
src_reg some_src_1 = src_reg(v, glsl_type::vec4_type);
|
||||
src_reg some_src_2 = src_reg(v, glsl_type::vec4_type);
|
||||
src_reg some_src_1 = src_reg(v, glsl_vec4_type());
|
||||
src_reg some_src_2 = src_reg(v, glsl_vec4_type());
|
||||
dst_reg init;
|
||||
|
||||
dst_reg m0 = dst_reg(MRF, 0);
|
||||
m0.writemask = WRITEMASK_Y;
|
||||
m0.type = BRW_REGISTER_TYPE_F;
|
||||
|
||||
dst_reg temp = dst_reg(v, glsl_type::float_type);
|
||||
dst_reg temp = dst_reg(v, glsl_float_type());
|
||||
|
||||
vec4_instruction *dp4 = v->emit(v->DP4(temp, some_src_1, some_src_2));
|
||||
v->emit(v->MOV(m0, src_reg(temp)));
|
||||
|
|
@ -206,12 +206,12 @@ TEST_F(register_coalesce_vec4_test, test_dp4_mrf)
|
|||
|
||||
TEST_F(register_coalesce_vec4_test, test_dp4_grf)
|
||||
{
|
||||
src_reg some_src_1 = src_reg(v, glsl_type::vec4_type);
|
||||
src_reg some_src_2 = src_reg(v, glsl_type::vec4_type);
|
||||
src_reg some_src_1 = src_reg(v, glsl_vec4_type());
|
||||
src_reg some_src_2 = src_reg(v, glsl_vec4_type());
|
||||
dst_reg init;
|
||||
|
||||
dst_reg to = dst_reg(v, glsl_type::vec4_type);
|
||||
dst_reg temp = dst_reg(v, glsl_type::float_type);
|
||||
dst_reg to = dst_reg(v, glsl_vec4_type());
|
||||
dst_reg temp = dst_reg(v, glsl_float_type());
|
||||
|
||||
vec4_instruction *dp4 = v->emit(v->DP4(temp, some_src_1, some_src_2));
|
||||
to.writemask = WRITEMASK_Y;
|
||||
|
|
@ -232,12 +232,12 @@ TEST_F(register_coalesce_vec4_test, test_dp4_grf)
|
|||
|
||||
TEST_F(register_coalesce_vec4_test, test_channel_mul_grf)
|
||||
{
|
||||
src_reg some_src_1 = src_reg(v, glsl_type::vec4_type);
|
||||
src_reg some_src_2 = src_reg(v, glsl_type::vec4_type);
|
||||
src_reg some_src_1 = src_reg(v, glsl_vec4_type());
|
||||
src_reg some_src_2 = src_reg(v, glsl_vec4_type());
|
||||
dst_reg init;
|
||||
|
||||
dst_reg to = dst_reg(v, glsl_type::vec4_type);
|
||||
dst_reg temp = dst_reg(v, glsl_type::float_type);
|
||||
dst_reg to = dst_reg(v, glsl_vec4_type());
|
||||
dst_reg temp = dst_reg(v, glsl_float_type());
|
||||
|
||||
vec4_instruction *mul = v->emit(v->MUL(temp, some_src_1, some_src_2));
|
||||
to.writemask = WRITEMASK_Y;
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue