mirror of
https://gitlab.freedesktop.org/mesa/mesa.git
synced 2026-05-05 05:18:08 +02:00
ilo: update genhw headers for media pipeline
Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
This commit is contained in:
Chia-I Wu
parent
207eccc5bf
commit
bfaed536dd
7 changed files with 479 additions and 148 deletions
|
|
@ -177,9 +177,13 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
|||
#define GEN6_MSG_DP_SEND_WRITE_COMMIT (0x1 << 17)
|
||||
#define GEN6_MSG_DP_OP__MASK 0x0001e000
|
||||
#define GEN6_MSG_DP_OP__SHIFT 13
|
||||
#define GEN6_MSG_DP_CTRL__MASK 0x00001f00
|
||||
#define GEN6_MSG_DP_CTRL__SHIFT 8
|
||||
#define GEN7_MSG_DP_CATEGORY (0x1 << 18)
|
||||
#define GEN7_MSG_DP_OP__MASK 0x0003c000
|
||||
#define GEN7_MSG_DP_OP__SHIFT 14
|
||||
#define GEN7_MSG_DP_CTRL__MASK 0x00003f00
|
||||
#define GEN7_MSG_DP_CTRL__SHIFT 8
|
||||
#define GEN7_MSG_DP_OWORD_BLOCK_READ_INVALIDATE (0x1 << 13)
|
||||
#define GEN6_MSG_DP_OWORD_BLOCK_SIZE__MASK 0x00000700
|
||||
#define GEN6_MSG_DP_OWORD_BLOCK_SIZE__SHIFT 8
|
||||
|
|
@ -214,7 +218,32 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
|||
#define GEN6_MSG_DP_RT_MODE_SIMD8_DUALSRC_HI (0x3 << 8)
|
||||
#define GEN6_MSG_DP_RT_MODE_SIMD8_LO (0x4 << 8)
|
||||
#define GEN6_MSG_DP_RT_MODE_SIMD8_IMAGE_WR (0x5 << 8)
|
||||
#define GEN7_MSG_DP_UNTYPED_MODE__MASK 0x00003000
|
||||
#define GEN7_MSG_DP_UNTYPED_MODE__SHIFT 12
|
||||
#define GEN7_MSG_DP_UNTYPED_MODE_SIMD4X2 (0x0 << 12)
|
||||
#define GEN7_MSG_DP_UNTYPED_MODE_SIMD16 (0x1 << 12)
|
||||
#define GEN7_MSG_DP_UNTYPED_MODE_SIMD8 (0x2 << 12)
|
||||
#define GEN7_MSG_DP_UNTYPED_MASK__MASK 0x00000f00
|
||||
#define GEN7_MSG_DP_UNTYPED_MASK__SHIFT 8
|
||||
#define GEN7_MSG_DP_UNTYPED_MASK_R (0x0 << 8)
|
||||
#define GEN7_MSG_DP_UNTYPED_MASK_G (0x1 << 8)
|
||||
#define GEN7_MSG_DP_UNTYPED_MASK_B (0x2 << 8)
|
||||
#define GEN7_MSG_DP_UNTYPED_MASK_A (0x4 << 8)
|
||||
#define GEN6_MSG_DP_SURFACE__MASK 0x000000ff
|
||||
#define GEN6_MSG_DP_SURFACE__SHIFT 0
|
||||
#define GEN6_MSG_TS_RESOURCE_SELECT__MASK 0x00000010
|
||||
#define GEN6_MSG_TS_RESOURCE_SELECT__SHIFT 4
|
||||
#define GEN6_MSG_TS_RESOURCE_SELECT_CHILD (0x0 << 4)
|
||||
#define GEN6_MSG_TS_RESOURCE_SELECT_ROOT (0x1 << 4)
|
||||
#define GEN6_MSG_TS_RESOURCE_SELECT_DEREF (0x0 << 4)
|
||||
#define GEN6_MSG_TS_RESOURCE_SELECT_NO_DEREF (0x1 << 4)
|
||||
#define GEN6_MSG_TS_REQUESTER_TYPE__MASK 0x00000002
|
||||
#define GEN6_MSG_TS_REQUESTER_TYPE__SHIFT 1
|
||||
#define GEN6_MSG_TS_REQUESTER_TYPE_ROOT (0x0 << 1)
|
||||
#define GEN6_MSG_TS_REQUESTER_TYPE_CHILD (0x1 << 1)
|
||||
#define GEN6_MSG_TS_OPCODE__MASK 0x00000001
|
||||
#define GEN6_MSG_TS_OPCODE__SHIFT 0
|
||||
#define GEN6_MSG_TS_OPCODE_DEREF 0x0
|
||||
#define GEN6_MSG_TS_OPCODE_SPAWN 0x1
|
||||
|
||||
#endif /* GEN_EU_MESSAGE_XML */
|
||||
|
|
|
|||
|
|
@ -95,6 +95,48 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
|||
#define GEN7_REG_SO_WRITE_OFFSET__ESIZE 0x8
|
||||
#define GEN7_REG_SO_WRITE_OFFSET__LEN 0x4
|
||||
|
||||
|
||||
#define GEN7_REG_L3SQCREG1 0xb010
|
||||
#define GEN7_REG_L3SQCREG1_CON4DCUNC (0x1 << 24)
|
||||
#define GEN7_REG_L3SQCREG1_SQGHPCI__MASK 0x00ff0000
|
||||
#define GEN7_REG_L3SQCREG1_SQGHPCI__SHIFT 16
|
||||
#define GEN7_REG_L3SQCREG1_SQGHPCI_18_6 (0x73 << 16)
|
||||
#define GEN75_REG_L3SQCREG1_SQGPCI__MASK 0x00f80000
|
||||
#define GEN75_REG_L3SQCREG1_SQGPCI__SHIFT 19
|
||||
#define GEN75_REG_L3SQCREG1_SQGPCI_24 (0xc << 19)
|
||||
#define GEN75_REG_L3SQCREG1_SQHPCI__MASK 0x0007c000
|
||||
#define GEN75_REG_L3SQCREG1_SQHPCI__SHIFT 14
|
||||
#define GEN75_REG_L3SQCREG1_SQHPCI_8 (0x4 << 14)
|
||||
|
||||
#define GEN7_REG_L3SQCREG2 0xb014
|
||||
|
||||
#define GEN7_REG_L3SQCREG3 0xb018
|
||||
|
||||
#define GEN7_REG_L3CNTLREG1 0xb01c
|
||||
|
||||
#define GEN7_REG_L3CNTLREG2 0xb020
|
||||
#define GEN7_REG_L3CNTLREG2_DCWASLMB (0x1 << 27)
|
||||
#define GEN7_REG_L3CNTLREG2_DCWASS__MASK 0x07e00000
|
||||
#define GEN7_REG_L3CNTLREG2_DCWASS__SHIFT 21
|
||||
#define GEN7_REG_L3CNTLREG2_ROCPSLMB (0x1 << 20)
|
||||
#define GEN7_REG_L3CNTLREG2_RDOCPL__MASK 0x000fc000
|
||||
#define GEN7_REG_L3CNTLREG2_RDOCPL__SHIFT 14
|
||||
#define GEN7_REG_L3CNTLREG2_URBSLMB (0x1 << 7)
|
||||
#define GEN7_REG_L3CNTLREG2_URBALL__MASK 0x0000007e
|
||||
#define GEN7_REG_L3CNTLREG2_URBALL__SHIFT 1
|
||||
#define GEN7_REG_L3CNTLREG2_SLMMENB (0x1 << 0)
|
||||
|
||||
#define GEN7_REG_L3CNTLREG3 0xb024
|
||||
#define GEN7_REG_L3CNTLREG3_TWALSLMB (0x1 << 21)
|
||||
#define GEN7_REG_L3CNTLREG3_TXWYALL__MASK 0x001f8000
|
||||
#define GEN7_REG_L3CNTLREG3_TXWYALL__SHIFT 15
|
||||
#define GEN7_REG_L3CNTLREG3_CWASLMB (0x1 << 14)
|
||||
#define GEN7_REG_L3CNTLREG3_CTWYALL__MASK 0x00003f00
|
||||
#define GEN7_REG_L3CNTLREG3_CTWYALL__SHIFT 8
|
||||
#define GEN7_REG_L3CNTLREG3_ISWYSLMB (0x1 << 7)
|
||||
#define GEN7_REG_L3CNTLREG3_ISWYALL__MASK 0x0000007e
|
||||
#define GEN7_REG_L3CNTLREG3_ISWYALL__SHIFT 1
|
||||
|
||||
#define GEN6_REG_BCS_SWCTRL 0x22200
|
||||
#define GEN6_REG_BCS_SWCTRL_DST_TILING_Y (0x1 << 1)
|
||||
#define GEN6_REG_BCS_SWCTRL_SRC_TILING_Y (0x1 << 0)
|
||||
|
|
|
|||
182
src/gallium/drivers/ilo/genhw/gen_render.xml.h
Normal file
182
src/gallium/drivers/ilo/genhw/gen_render.xml.h
Normal file
|
|
@ -0,0 +1,182 @@
|
|||
#ifndef GEN_RENDER_XML
|
||||
#define GEN_RENDER_XML
|
||||
|
||||
/* Autogenerated file, DO NOT EDIT manually!
|
||||
|
||||
This file was generated by the rules-ng-ng headergen tool in this git repository:
|
||||
https://github.com/olvaffe/envytools/
|
||||
git clone https://github.com/olvaffe/envytools.git
|
||||
|
||||
Copyright (C) 2014 by the following authors:
|
||||
- Chia-I Wu <olvaffe@gmail.com> (olv)
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining
|
||||
a copy of this software and associated documentation files (the
|
||||
"Software"), to deal in the Software without restriction, including
|
||||
without limitation the rights to use, copy, modify, merge, publish,
|
||||
distribute, sublicense, and/or sell copies of the Software, and to
|
||||
permit persons to whom the Software is furnished to do so, subject to
|
||||
the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice (including the
|
||||
next paragraph) shall be included in all copies or substantial
|
||||
portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
|
||||
LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
|
||||
OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
|
||||
WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
#define GEN6_RENDER_TYPE__MASK 0xe0000000
|
||||
#define GEN6_RENDER_TYPE__SHIFT 29
|
||||
#define GEN6_RENDER_TYPE_RENDER (0x3 << 29)
|
||||
#define GEN6_RENDER_SUBTYPE__MASK 0x18000000
|
||||
#define GEN6_RENDER_SUBTYPE__SHIFT 27
|
||||
#define GEN6_RENDER_SUBTYPE_COMMON (0x0 << 27)
|
||||
#define GEN6_RENDER_SUBTYPE_SINGLE_DW (0x1 << 27)
|
||||
#define GEN6_RENDER_SUBTYPE_MEDIA (0x2 << 27)
|
||||
#define GEN6_RENDER_SUBTYPE_3D (0x3 << 27)
|
||||
#define GEN6_RENDER_OPCODE__MASK 0x07ff0000
|
||||
#define GEN6_RENDER_OPCODE__SHIFT 16
|
||||
#define GEN6_RENDER_OPCODE_STATE_BASE_ADDRESS (0x101 << 16)
|
||||
#define GEN6_RENDER_OPCODE_STATE_SIP (0x102 << 16)
|
||||
#define GEN6_RENDER_OPCODE_3DSTATE_VF_STATISTICS (0xb << 16)
|
||||
#define GEN6_RENDER_OPCODE_PIPELINE_SELECT (0x104 << 16)
|
||||
#define GEN6_RENDER_OPCODE_MEDIA_VFE_STATE (0x0 << 16)
|
||||
#define GEN6_RENDER_OPCODE_MEDIA_CURBE_LOAD (0x1 << 16)
|
||||
#define GEN6_RENDER_OPCODE_MEDIA_INTERFACE_DESCRIPTOR_LOAD (0x2 << 16)
|
||||
#define GEN6_RENDER_OPCODE_MEDIA_STATE_FLUSH (0x4 << 16)
|
||||
#define GEN7_RENDER_OPCODE_GPGPU_WALKER (0x105 << 16)
|
||||
#define GEN6_RENDER_OPCODE_3DSTATE_BINDING_TABLE_POINTERS (0x1 << 16)
|
||||
#define GEN6_RENDER_OPCODE_3DSTATE_SAMPLER_STATE_POINTERS (0x2 << 16)
|
||||
#define GEN7_RENDER_OPCODE_3DSTATE_CLEAR_PARAMS (0x4 << 16)
|
||||
#define GEN6_RENDER_OPCODE_3DSTATE_URB (0x5 << 16)
|
||||
#define GEN7_RENDER_OPCODE_3DSTATE_DEPTH_BUFFER (0x5 << 16)
|
||||
#define GEN7_RENDER_OPCODE_3DSTATE_STENCIL_BUFFER (0x6 << 16)
|
||||
#define GEN7_RENDER_OPCODE_3DSTATE_HIER_DEPTH_BUFFER (0x7 << 16)
|
||||
#define GEN6_RENDER_OPCODE_3DSTATE_VERTEX_BUFFERS (0x8 << 16)
|
||||
#define GEN6_RENDER_OPCODE_3DSTATE_VERTEX_ELEMENTS (0x9 << 16)
|
||||
#define GEN6_RENDER_OPCODE_3DSTATE_INDEX_BUFFER (0xa << 16)
|
||||
#define GEN75_RENDER_OPCODE_3DSTATE_VF (0xc << 16)
|
||||
#define GEN6_RENDER_OPCODE_3DSTATE_VIEWPORT_STATE_POINTERS (0xd << 16)
|
||||
#define GEN6_RENDER_OPCODE_3DSTATE_CC_STATE_POINTERS (0xe << 16)
|
||||
#define GEN6_RENDER_OPCODE_3DSTATE_SCISSOR_STATE_POINTERS (0xf << 16)
|
||||
#define GEN6_RENDER_OPCODE_3DSTATE_VS (0x10 << 16)
|
||||
#define GEN6_RENDER_OPCODE_3DSTATE_GS (0x11 << 16)
|
||||
#define GEN6_RENDER_OPCODE_3DSTATE_CLIP (0x12 << 16)
|
||||
#define GEN6_RENDER_OPCODE_3DSTATE_SF (0x13 << 16)
|
||||
#define GEN6_RENDER_OPCODE_3DSTATE_WM (0x14 << 16)
|
||||
#define GEN6_RENDER_OPCODE_3DSTATE_CONSTANT_VS (0x15 << 16)
|
||||
#define GEN6_RENDER_OPCODE_3DSTATE_CONSTANT_GS (0x16 << 16)
|
||||
#define GEN6_RENDER_OPCODE_3DSTATE_CONSTANT_PS (0x17 << 16)
|
||||
#define GEN6_RENDER_OPCODE_3DSTATE_SAMPLE_MASK (0x18 << 16)
|
||||
#define GEN7_RENDER_OPCODE_3DSTATE_CONSTANT_HS (0x19 << 16)
|
||||
#define GEN7_RENDER_OPCODE_3DSTATE_CONSTANT_DS (0x1a << 16)
|
||||
#define GEN7_RENDER_OPCODE_3DSTATE_HS (0x1b << 16)
|
||||
#define GEN7_RENDER_OPCODE_3DSTATE_TE (0x1c << 16)
|
||||
#define GEN7_RENDER_OPCODE_3DSTATE_DS (0x1d << 16)
|
||||
#define GEN7_RENDER_OPCODE_3DSTATE_STREAMOUT (0x1e << 16)
|
||||
#define GEN7_RENDER_OPCODE_3DSTATE_SBE (0x1f << 16)
|
||||
#define GEN7_RENDER_OPCODE_3DSTATE_PS (0x20 << 16)
|
||||
#define GEN7_RENDER_OPCODE_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP (0x21 << 16)
|
||||
#define GEN7_RENDER_OPCODE_3DSTATE_VIEWPORT_STATE_POINTERS_CC (0x23 << 16)
|
||||
#define GEN7_RENDER_OPCODE_3DSTATE_BLEND_STATE_POINTERS (0x24 << 16)
|
||||
#define GEN7_RENDER_OPCODE_3DSTATE_DEPTH_STENCIL_STATE_POINTERS (0x25 << 16)
|
||||
#define GEN7_RENDER_OPCODE_3DSTATE_BINDING_TABLE_POINTERS_VS (0x26 << 16)
|
||||
#define GEN7_RENDER_OPCODE_3DSTATE_BINDING_TABLE_POINTERS_HS (0x27 << 16)
|
||||
#define GEN7_RENDER_OPCODE_3DSTATE_BINDING_TABLE_POINTERS_DS (0x28 << 16)
|
||||
#define GEN7_RENDER_OPCODE_3DSTATE_BINDING_TABLE_POINTERS_GS (0x29 << 16)
|
||||
#define GEN7_RENDER_OPCODE_3DSTATE_BINDING_TABLE_POINTERS_PS (0x2a << 16)
|
||||
#define GEN7_RENDER_OPCODE_3DSTATE_SAMPLER_STATE_POINTERS_VS (0x2b << 16)
|
||||
#define GEN7_RENDER_OPCODE_3DSTATE_SAMPLER_STATE_POINTERS_HS (0x2c << 16)
|
||||
#define GEN7_RENDER_OPCODE_3DSTATE_SAMPLER_STATE_POINTERS_DS (0x2d << 16)
|
||||
#define GEN7_RENDER_OPCODE_3DSTATE_SAMPLER_STATE_POINTERS_GS (0x2e << 16)
|
||||
#define GEN7_RENDER_OPCODE_3DSTATE_SAMPLER_STATE_POINTERS_PS (0x2f << 16)
|
||||
#define GEN7_RENDER_OPCODE_3DSTATE_URB_VS (0x30 << 16)
|
||||
#define GEN7_RENDER_OPCODE_3DSTATE_URB_HS (0x31 << 16)
|
||||
#define GEN7_RENDER_OPCODE_3DSTATE_URB_DS (0x32 << 16)
|
||||
#define GEN7_RENDER_OPCODE_3DSTATE_URB_GS (0x33 << 16)
|
||||
#define GEN6_RENDER_OPCODE_3DSTATE_DRAWING_RECTANGLE (0x100 << 16)
|
||||
#define GEN6_RENDER_OPCODE_3DSTATE_DEPTH_BUFFER (0x105 << 16)
|
||||
#define GEN6_RENDER_OPCODE_3DSTATE_POLY_STIPPLE_OFFSET (0x106 << 16)
|
||||
#define GEN6_RENDER_OPCODE_3DSTATE_POLY_STIPPLE_PATTERN (0x107 << 16)
|
||||
#define GEN6_RENDER_OPCODE_3DSTATE_LINE_STIPPLE (0x108 << 16)
|
||||
#define GEN6_RENDER_OPCODE_3DSTATE_AA_LINE_PARAMETERS (0x10a << 16)
|
||||
#define GEN6_RENDER_OPCODE_3DSTATE_GS_SVB_INDEX (0x10b << 16)
|
||||
#define GEN6_RENDER_OPCODE_3DSTATE_MULTISAMPLE (0x10d << 16)
|
||||
#define GEN6_RENDER_OPCODE_3DSTATE_STENCIL_BUFFER (0x10e << 16)
|
||||
#define GEN6_RENDER_OPCODE_3DSTATE_HIER_DEPTH_BUFFER (0x10f << 16)
|
||||
#define GEN6_RENDER_OPCODE_3DSTATE_CLEAR_PARAMS (0x110 << 16)
|
||||
#define GEN7_RENDER_OPCODE_3DSTATE_PUSH_CONSTANT_ALLOC_VS (0x112 << 16)
|
||||
#define GEN7_RENDER_OPCODE_3DSTATE_PUSH_CONSTANT_ALLOC_HS (0x113 << 16)
|
||||
#define GEN7_RENDER_OPCODE_3DSTATE_PUSH_CONSTANT_ALLOC_DS (0x114 << 16)
|
||||
#define GEN7_RENDER_OPCODE_3DSTATE_PUSH_CONSTANT_ALLOC_GS (0x115 << 16)
|
||||
#define GEN7_RENDER_OPCODE_3DSTATE_PUSH_CONSTANT_ALLOC_PS (0x116 << 16)
|
||||
#define GEN7_RENDER_OPCODE_3DSTATE_SO_DECL_LIST (0x117 << 16)
|
||||
#define GEN7_RENDER_OPCODE_3DSTATE_SO_BUFFER (0x118 << 16)
|
||||
#define GEN6_RENDER_OPCODE_PIPE_CONTROL (0x200 << 16)
|
||||
#define GEN6_RENDER_OPCODE_3DPRIMITIVE (0x300 << 16)
|
||||
#define GEN6_RENDER_LENGTH__MASK 0x000000ff
|
||||
#define GEN6_RENDER_LENGTH__SHIFT 0
|
||||
#define GEN6_MOCS_LLC__MASK 0x00000003
|
||||
#define GEN6_MOCS_LLC__SHIFT 0
|
||||
#define GEN6_MOCS_LLC_PTE 0x0
|
||||
#define GEN6_MOCS_LLC_UC 0x1
|
||||
#define GEN6_MOCS_LLC_ON 0x2
|
||||
#define GEN7_MOCS_LLC__MASK 0x00000002
|
||||
#define GEN7_MOCS_LLC__SHIFT 1
|
||||
#define GEN7_MOCS_LLC_PTE (0x0 << 1)
|
||||
#define GEN7_MOCS_LLC_ON (0x1 << 1)
|
||||
#define GEN75_MOCS_LLC__MASK 0x00000006
|
||||
#define GEN75_MOCS_LLC__SHIFT 1
|
||||
#define GEN75_MOCS_LLC_PTE (0x0 << 1)
|
||||
#define GEN75_MOCS_LLC_UC (0x1 << 1)
|
||||
#define GEN75_MOCS_LLC_ON (0x2 << 1)
|
||||
#define GEN75_MOCS_LLC_ELLC (0x3 << 1)
|
||||
#define GEN7_MOCS_L3__MASK 0x00000001
|
||||
#define GEN7_MOCS_L3__SHIFT 0
|
||||
#define GEN7_MOCS_L3_UC 0x0
|
||||
#define GEN7_MOCS_L3_ON 0x1
|
||||
#define GEN6_BASE_ADDR__MASK 0xfffff000
|
||||
#define GEN6_BASE_ADDR__SHIFT 12
|
||||
#define GEN6_BASE_ADDR__SHR 12
|
||||
#define GEN6_BASE_ADDR_MOCS__MASK 0x00000f00
|
||||
#define GEN6_BASE_ADDR_MOCS__SHIFT 8
|
||||
#define GEN6_BASE_ADDR_MODIFIED (0x1 << 0)
|
||||
#define GEN6_STATE_BASE_ADDRESS__SIZE 10
|
||||
|
||||
|
||||
#define GEN6_BASE_ADDR_DW1_GENERAL_STATELESS_MOCS__MASK 0x000000f0
|
||||
#define GEN6_BASE_ADDR_DW1_GENERAL_STATELESS_MOCS__SHIFT 4
|
||||
#define GEN6_BASE_ADDR_DW1_GENERAL_STATELESS_FORCE_WRITE_THRU (0x1 << 3)
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#define GEN6_STATE_SIP__SIZE 2
|
||||
|
||||
|
||||
#define GEN6_SIP_DW1_KERNEL_ADDR__MASK 0xfffffff0
|
||||
#define GEN6_SIP_DW1_KERNEL_ADDR__SHIFT 4
|
||||
#define GEN6_SIP_DW1_KERNEL_ADDR__SHR 4
|
||||
|
||||
#define GEN6_PIPELINE_SELECT__SIZE 1
|
||||
|
||||
#define GEN6_PIPELINE_SELECT_DW0_SELECT__MASK 0x00000003
|
||||
#define GEN6_PIPELINE_SELECT_DW0_SELECT__SHIFT 0
|
||||
#define GEN6_PIPELINE_SELECT_DW0_SELECT_3D 0x0
|
||||
#define GEN6_PIPELINE_SELECT_DW0_SELECT_MEDIA 0x1
|
||||
#define GEN7_PIPELINE_SELECT_DW0_SELECT_GPGPU 0x2
|
||||
|
||||
|
||||
#endif /* GEN_RENDER_XML */
|
||||
|
|
@ -109,99 +109,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
|||
#define GEN6_ZFORMAT_D24_UNORM_S8_UINT 0x2
|
||||
#define GEN6_ZFORMAT_D24_UNORM_X8_UINT 0x3
|
||||
#define GEN6_ZFORMAT_D16_UNORM 0x5
|
||||
#define GEN6_RENDER_TYPE__MASK 0xe0000000
|
||||
#define GEN6_RENDER_TYPE__SHIFT 29
|
||||
#define GEN6_RENDER_TYPE_RENDER (0x3 << 29)
|
||||
#define GEN6_RENDER_SUBTYPE__MASK 0x18000000
|
||||
#define GEN6_RENDER_SUBTYPE__SHIFT 27
|
||||
#define GEN6_RENDER_SUBTYPE_COMMON (0x0 << 27)
|
||||
#define GEN6_RENDER_SUBTYPE_SINGLE_DW (0x1 << 27)
|
||||
#define GEN6_RENDER_SUBTYPE_MEDIA (0x2 << 27)
|
||||
#define GEN6_RENDER_SUBTYPE_3D (0x3 << 27)
|
||||
#define GEN6_RENDER_OPCODE__MASK 0x07ff0000
|
||||
#define GEN6_RENDER_OPCODE__SHIFT 16
|
||||
#define GEN6_RENDER_OPCODE_STATE_BASE_ADDRESS (0x101 << 16)
|
||||
#define GEN6_RENDER_OPCODE_STATE_SIP (0x102 << 16)
|
||||
#define GEN6_RENDER_OPCODE_3DSTATE_VF_STATISTICS (0xb << 16)
|
||||
#define GEN6_RENDER_OPCODE_PIPELINE_SELECT (0x104 << 16)
|
||||
#define GEN6_RENDER_OPCODE_MEDIA_VFE_STATE (0x0 << 16)
|
||||
#define GEN6_RENDER_OPCODE_MEDIA_CURBE_LOAD (0x1 << 16)
|
||||
#define GEN6_RENDER_OPCODE_MEDIA_INTERFACE_DESCRIPTOR_LOAD (0x2 << 16)
|
||||
#define GEN6_RENDER_OPCODE_MEDIA_GATEWAY_STATE (0x3 << 16)
|
||||
#define GEN6_RENDER_OPCODE_MEDIA_STATE_FLUSH (0x4 << 16)
|
||||
#define GEN6_RENDER_OPCODE_MEDIA_OBJECT_WALKER (0x103 << 16)
|
||||
#define GEN7_RENDER_OPCODE_GPGPU_WALKER (0x105 << 16)
|
||||
#define GEN6_RENDER_OPCODE_3DSTATE_BINDING_TABLE_POINTERS (0x1 << 16)
|
||||
#define GEN6_RENDER_OPCODE_3DSTATE_SAMPLER_STATE_POINTERS (0x2 << 16)
|
||||
#define GEN7_RENDER_OPCODE_3DSTATE_CLEAR_PARAMS (0x4 << 16)
|
||||
#define GEN6_RENDER_OPCODE_3DSTATE_URB (0x5 << 16)
|
||||
#define GEN7_RENDER_OPCODE_3DSTATE_DEPTH_BUFFER (0x5 << 16)
|
||||
#define GEN7_RENDER_OPCODE_3DSTATE_STENCIL_BUFFER (0x6 << 16)
|
||||
#define GEN7_RENDER_OPCODE_3DSTATE_HIER_DEPTH_BUFFER (0x7 << 16)
|
||||
#define GEN6_RENDER_OPCODE_3DSTATE_VERTEX_BUFFERS (0x8 << 16)
|
||||
#define GEN6_RENDER_OPCODE_3DSTATE_VERTEX_ELEMENTS (0x9 << 16)
|
||||
#define GEN6_RENDER_OPCODE_3DSTATE_INDEX_BUFFER (0xa << 16)
|
||||
#define GEN75_RENDER_OPCODE_3DSTATE_VF (0xc << 16)
|
||||
#define GEN6_RENDER_OPCODE_3DSTATE_VIEWPORT_STATE_POINTERS (0xd << 16)
|
||||
#define GEN6_RENDER_OPCODE_3DSTATE_CC_STATE_POINTERS (0xe << 16)
|
||||
#define GEN6_RENDER_OPCODE_3DSTATE_SCISSOR_STATE_POINTERS (0xf << 16)
|
||||
#define GEN6_RENDER_OPCODE_3DSTATE_VS (0x10 << 16)
|
||||
#define GEN6_RENDER_OPCODE_3DSTATE_GS (0x11 << 16)
|
||||
#define GEN6_RENDER_OPCODE_3DSTATE_CLIP (0x12 << 16)
|
||||
#define GEN6_RENDER_OPCODE_3DSTATE_SF (0x13 << 16)
|
||||
#define GEN6_RENDER_OPCODE_3DSTATE_WM (0x14 << 16)
|
||||
#define GEN6_RENDER_OPCODE_3DSTATE_CONSTANT_VS (0x15 << 16)
|
||||
#define GEN6_RENDER_OPCODE_3DSTATE_CONSTANT_GS (0x16 << 16)
|
||||
#define GEN6_RENDER_OPCODE_3DSTATE_CONSTANT_PS (0x17 << 16)
|
||||
#define GEN6_RENDER_OPCODE_3DSTATE_SAMPLE_MASK (0x18 << 16)
|
||||
#define GEN7_RENDER_OPCODE_3DSTATE_CONSTANT_HS (0x19 << 16)
|
||||
#define GEN7_RENDER_OPCODE_3DSTATE_CONSTANT_DS (0x1a << 16)
|
||||
#define GEN7_RENDER_OPCODE_3DSTATE_HS (0x1b << 16)
|
||||
#define GEN7_RENDER_OPCODE_3DSTATE_TE (0x1c << 16)
|
||||
#define GEN7_RENDER_OPCODE_3DSTATE_DS (0x1d << 16)
|
||||
#define GEN7_RENDER_OPCODE_3DSTATE_STREAMOUT (0x1e << 16)
|
||||
#define GEN7_RENDER_OPCODE_3DSTATE_SBE (0x1f << 16)
|
||||
#define GEN7_RENDER_OPCODE_3DSTATE_PS (0x20 << 16)
|
||||
#define GEN7_RENDER_OPCODE_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP (0x21 << 16)
|
||||
#define GEN7_RENDER_OPCODE_3DSTATE_VIEWPORT_STATE_POINTERS_CC (0x23 << 16)
|
||||
#define GEN7_RENDER_OPCODE_3DSTATE_BLEND_STATE_POINTERS (0x24 << 16)
|
||||
#define GEN7_RENDER_OPCODE_3DSTATE_DEPTH_STENCIL_STATE_POINTERS (0x25 << 16)
|
||||
#define GEN7_RENDER_OPCODE_3DSTATE_BINDING_TABLE_POINTERS_VS (0x26 << 16)
|
||||
#define GEN7_RENDER_OPCODE_3DSTATE_BINDING_TABLE_POINTERS_HS (0x27 << 16)
|
||||
#define GEN7_RENDER_OPCODE_3DSTATE_BINDING_TABLE_POINTERS_DS (0x28 << 16)
|
||||
#define GEN7_RENDER_OPCODE_3DSTATE_BINDING_TABLE_POINTERS_GS (0x29 << 16)
|
||||
#define GEN7_RENDER_OPCODE_3DSTATE_BINDING_TABLE_POINTERS_PS (0x2a << 16)
|
||||
#define GEN7_RENDER_OPCODE_3DSTATE_SAMPLER_STATE_POINTERS_VS (0x2b << 16)
|
||||
#define GEN7_RENDER_OPCODE_3DSTATE_SAMPLER_STATE_POINTERS_HS (0x2c << 16)
|
||||
#define GEN7_RENDER_OPCODE_3DSTATE_SAMPLER_STATE_POINTERS_DS (0x2d << 16)
|
||||
#define GEN7_RENDER_OPCODE_3DSTATE_SAMPLER_STATE_POINTERS_GS (0x2e << 16)
|
||||
#define GEN7_RENDER_OPCODE_3DSTATE_SAMPLER_STATE_POINTERS_PS (0x2f << 16)
|
||||
#define GEN7_RENDER_OPCODE_3DSTATE_URB_VS (0x30 << 16)
|
||||
#define GEN7_RENDER_OPCODE_3DSTATE_URB_HS (0x31 << 16)
|
||||
#define GEN7_RENDER_OPCODE_3DSTATE_URB_DS (0x32 << 16)
|
||||
#define GEN7_RENDER_OPCODE_3DSTATE_URB_GS (0x33 << 16)
|
||||
#define GEN6_RENDER_OPCODE_3DSTATE_DRAWING_RECTANGLE (0x100 << 16)
|
||||
#define GEN6_RENDER_OPCODE_3DSTATE_DEPTH_BUFFER (0x105 << 16)
|
||||
#define GEN6_RENDER_OPCODE_3DSTATE_POLY_STIPPLE_OFFSET (0x106 << 16)
|
||||
#define GEN6_RENDER_OPCODE_3DSTATE_POLY_STIPPLE_PATTERN (0x107 << 16)
|
||||
#define GEN6_RENDER_OPCODE_3DSTATE_LINE_STIPPLE (0x108 << 16)
|
||||
#define GEN6_RENDER_OPCODE_3DSTATE_AA_LINE_PARAMETERS (0x10a << 16)
|
||||
#define GEN6_RENDER_OPCODE_3DSTATE_GS_SVB_INDEX (0x10b << 16)
|
||||
#define GEN6_RENDER_OPCODE_3DSTATE_MULTISAMPLE (0x10d << 16)
|
||||
#define GEN6_RENDER_OPCODE_3DSTATE_STENCIL_BUFFER (0x10e << 16)
|
||||
#define GEN6_RENDER_OPCODE_3DSTATE_HIER_DEPTH_BUFFER (0x10f << 16)
|
||||
#define GEN6_RENDER_OPCODE_3DSTATE_CLEAR_PARAMS (0x110 << 16)
|
||||
#define GEN7_RENDER_OPCODE_3DSTATE_PUSH_CONSTANT_ALLOC_VS (0x112 << 16)
|
||||
#define GEN7_RENDER_OPCODE_3DSTATE_PUSH_CONSTANT_ALLOC_HS (0x113 << 16)
|
||||
#define GEN7_RENDER_OPCODE_3DSTATE_PUSH_CONSTANT_ALLOC_DS (0x114 << 16)
|
||||
#define GEN7_RENDER_OPCODE_3DSTATE_PUSH_CONSTANT_ALLOC_GS (0x115 << 16)
|
||||
#define GEN7_RENDER_OPCODE_3DSTATE_PUSH_CONSTANT_ALLOC_PS (0x116 << 16)
|
||||
#define GEN7_RENDER_OPCODE_3DSTATE_SO_DECL_LIST (0x117 << 16)
|
||||
#define GEN7_RENDER_OPCODE_3DSTATE_SO_BUFFER (0x118 << 16)
|
||||
#define GEN6_RENDER_OPCODE_PIPE_CONTROL (0x200 << 16)
|
||||
#define GEN6_RENDER_OPCODE_3DPRIMITIVE (0x300 << 16)
|
||||
#define GEN6_RENDER_LENGTH__MASK 0x000000ff
|
||||
#define GEN6_RENDER_LENGTH__SHIFT 0
|
||||
#define GEN6_INTERP_NONPERSPECTIVE_SAMPLE (0x1 << 5)
|
||||
#define GEN6_INTERP_NONPERSPECTIVE_CENTROID (0x1 << 4)
|
||||
#define GEN6_INTERP_NONPERSPECTIVE_PIXEL (0x1 << 3)
|
||||
|
|
@ -235,46 +142,10 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
|||
#define GEN6_THREADSCRATCH_ADDR__SHR 10
|
||||
#define GEN6_THREADSCRATCH_SPACE_PER_THREAD__MASK 0x0000000f
|
||||
#define GEN6_THREADSCRATCH_SPACE_PER_THREAD__SHIFT 0
|
||||
#define GEN6_BASE_ADDR__MASK 0xfffff000
|
||||
#define GEN6_BASE_ADDR__SHIFT 12
|
||||
#define GEN6_BASE_ADDR__SHR 12
|
||||
#define GEN6_BASE_ADDR_MOCS__MASK 0x00000f00
|
||||
#define GEN6_BASE_ADDR_MOCS__SHIFT 8
|
||||
#define GEN6_BASE_ADDR_MODIFIED (0x1 << 0)
|
||||
#define GEN6_STATE_BASE_ADDRESS__SIZE 10
|
||||
|
||||
|
||||
#define GEN6_BASE_ADDR_DW1_GENERAL_STATELESS_MOCS__MASK 0x000000f0
|
||||
#define GEN6_BASE_ADDR_DW1_GENERAL_STATELESS_MOCS__SHIFT 4
|
||||
#define GEN6_BASE_ADDR_DW1_GENERAL_STATELESS_FORCE_WRITE_THRU (0x1 << 3)
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#define GEN6_STATE_SIP__SIZE 2
|
||||
|
||||
|
||||
#define GEN6_SIP_DW1_KERNEL_ADDR__MASK 0xfffffff0
|
||||
#define GEN6_SIP_DW1_KERNEL_ADDR__SHIFT 4
|
||||
#define GEN6_SIP_DW1_KERNEL_ADDR__SHR 4
|
||||
|
||||
#define GEN6_3DSTATE_VF_STATISTICS__SIZE 1
|
||||
|
||||
#define GEN6_VF_STATS_DW0_ENABLE (0x1 << 0)
|
||||
|
||||
#define GEN6_PIPELINE_SELECT__SIZE 1
|
||||
|
||||
#define GEN6_PIPELINE_SELECT_DW0_SELECT__MASK 0x00000003
|
||||
#define GEN6_PIPELINE_SELECT_DW0_SELECT__SHIFT 0
|
||||
#define GEN6_PIPELINE_SELECT_DW0_SELECT_3D 0x0
|
||||
#define GEN6_PIPELINE_SELECT_DW0_SELECT_MEDIA 0x1
|
||||
#define GEN75_PIPELINE_SELECT_DW0_SELECT_GPGPU 0x2
|
||||
|
||||
#define GEN6_3DSTATE_BINDING_TABLE_POINTERS__SIZE 4
|
||||
|
||||
#define GEN6_PTR_BINDING_TABLE_DW0_PS_CHANGED (0x1 << 12)
|
||||
|
|
|
|||
224
src/gallium/drivers/ilo/genhw/gen_render_media.xml.h
Normal file
224
src/gallium/drivers/ilo/genhw/gen_render_media.xml.h
Normal file
|
|
@ -0,0 +1,224 @@
|
|||
#ifndef GEN_RENDER_MEDIA_XML
|
||||
#define GEN_RENDER_MEDIA_XML
|
||||
|
||||
/* Autogenerated file, DO NOT EDIT manually!
|
||||
|
||||
This file was generated by the rules-ng-ng headergen tool in this git repository:
|
||||
https://github.com/olvaffe/envytools/
|
||||
git clone https://github.com/olvaffe/envytools.git
|
||||
|
||||
Copyright (C) 2014 by the following authors:
|
||||
- Chia-I Wu <olvaffe@gmail.com> (olv)
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining
|
||||
a copy of this software and associated documentation files (the
|
||||
"Software"), to deal in the Software without restriction, including
|
||||
without limitation the rights to use, copy, modify, merge, publish,
|
||||
distribute, sublicense, and/or sell copies of the Software, and to
|
||||
permit persons to whom the Software is furnished to do so, subject to
|
||||
the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice (including the
|
||||
next paragraph) shall be included in all copies or substantial
|
||||
portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
|
||||
LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
|
||||
OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
|
||||
WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
#define GEN6_INTERFACE_DESCRIPTOR_DATA__SIZE 8
|
||||
|
||||
#define GEN6_IDRT_DW0_KERNEL_ADDR__MASK 0xffffffc0
|
||||
#define GEN6_IDRT_DW0_KERNEL_ADDR__SHIFT 6
|
||||
#define GEN6_IDRT_DW0_KERNEL_ADDR__SHR 6
|
||||
|
||||
#define GEN6_IDRT_DW1_SPF (0x1 << 18)
|
||||
#define GEN6_IDRT_DW1_PRIORITY_HIGH (0x1 << 17)
|
||||
#define GEN6_IDRT_DW1_FP_MODE_ALT (0x1 << 16)
|
||||
#define GEN6_IDRT_DW1_ILLEGAL_CODE_EXCEPTION (0x1 << 13)
|
||||
#define GEN6_IDRT_DW1_MASK_STACK_EXCEPTION (0x1 << 11)
|
||||
#define GEN6_IDRT_DW1_SOFTWARE_EXCEPTION (0x1 << 7)
|
||||
|
||||
#define GEN6_IDRT_DW2_SAMPLER_ADDR__MASK 0xffffffe0
|
||||
#define GEN6_IDRT_DW2_SAMPLER_ADDR__SHIFT 5
|
||||
#define GEN6_IDRT_DW2_SAMPLER_ADDR__SHR 5
|
||||
#define GEN6_IDRT_DW2_SAMPLER_COUNT__MASK 0x0000001c
|
||||
#define GEN6_IDRT_DW2_SAMPLER_COUNT__SHIFT 2
|
||||
|
||||
#define GEN6_IDRT_DW3_BINDING_TABLE_ADDR__MASK 0x0000ffe0
|
||||
#define GEN6_IDRT_DW3_BINDING_TABLE_ADDR__SHIFT 5
|
||||
#define GEN6_IDRT_DW3_BINDING_TABLE_ADDR__SHR 5
|
||||
#define GEN6_IDRT_DW3_BINDING_TABLE_SIZE__MASK 0x0000001f
|
||||
#define GEN6_IDRT_DW3_BINDING_TABLE_SIZE__SHIFT 0
|
||||
|
||||
#define GEN6_IDRT_DW4_CURBE_READ_LEN__MASK 0xffff0000
|
||||
#define GEN6_IDRT_DW4_CURBE_READ_LEN__SHIFT 16
|
||||
#define GEN6_IDRT_DW4_CURBE_READ_OFFSET__MASK 0x0000ffff
|
||||
#define GEN6_IDRT_DW4_CURBE_READ_OFFSET__SHIFT 0
|
||||
|
||||
#define GEN6_IDRT_DW5_BARRIER_ID__MASK 0x0000000f
|
||||
#define GEN6_IDRT_DW5_BARRIER_ID__SHIFT 0
|
||||
|
||||
#define GEN7_IDRT_DW5_BARRIER_RETURN_GRF__MASK 0xff000000
|
||||
#define GEN7_IDRT_DW5_BARRIER_RETURN_GRF__SHIFT 24
|
||||
#define GEN7_IDRT_DW5_ROUNDING_MODE__MASK 0x00c00000
|
||||
#define GEN7_IDRT_DW5_ROUNDING_MODE__SHIFT 22
|
||||
#define GEN7_IDRT_DW5_ROUNDING_MODE_RTNE (0x0 << 22)
|
||||
#define GEN7_IDRT_DW5_ROUNDING_MODE_RU (0x1 << 22)
|
||||
#define GEN7_IDRT_DW5_ROUNDING_MODE_RD (0x2 << 22)
|
||||
#define GEN7_IDRT_DW5_ROUNDING_MODE_RTZ (0x3 << 22)
|
||||
#define GEN7_IDRT_DW5_BARRIER_ENABLE (0x1 << 21)
|
||||
#define GEN7_IDRT_DW5_SLM_SIZE__MASK 0x001f0000
|
||||
#define GEN7_IDRT_DW5_SLM_SIZE__SHIFT 16
|
||||
#define GEN7_IDRT_DW5_BARRIER_RETURN_BYTE__MASK 0x0000ff00
|
||||
#define GEN7_IDRT_DW5_BARRIER_RETURN_BYTE__SHIFT 8
|
||||
#define GEN7_IDRT_DW5_THREAD_GROUP_SIZE__MASK 0x000000ff
|
||||
#define GEN7_IDRT_DW5_THREAD_GROUP_SIZE__SHIFT 0
|
||||
|
||||
#define GEN75_IDRT_DW6_CROSS_THREAD_CURBE_READ_LEN__MASK 0x000000ff
|
||||
#define GEN75_IDRT_DW6_CROSS_THREAD_CURBE_READ_LEN__SHIFT 0
|
||||
|
||||
|
||||
#define GEN6_MEDIA_VFE_STATE__SIZE 8
|
||||
|
||||
|
||||
#define GEN6_VFE_DW1_SCRATCH_ADDR__MASK 0xfffffc00
|
||||
#define GEN6_VFE_DW1_SCRATCH_ADDR__SHIFT 10
|
||||
#define GEN6_VFE_DW1_SCRATCH_ADDR__SHR 10
|
||||
#define GEN6_VFE_DW1_SCRATCH_STACK_SIZE__MASK 0x000000f0
|
||||
#define GEN6_VFE_DW1_SCRATCH_STACK_SIZE__SHIFT 4
|
||||
#define GEN6_VFE_DW1_SCRATCH_SPACE_PER_THREAD__MASK 0x0000000f
|
||||
#define GEN6_VFE_DW1_SCRATCH_SPACE_PER_THREAD__SHIFT 0
|
||||
|
||||
#define GEN6_VFE_DW2_MAX_THREADS__MASK 0xffff0000
|
||||
#define GEN6_VFE_DW2_MAX_THREADS__SHIFT 16
|
||||
#define GEN6_VFE_DW2_URB_ENTRY_COUNT__MASK 0x0000ff00
|
||||
#define GEN6_VFE_DW2_URB_ENTRY_COUNT__SHIFT 8
|
||||
#define GEN6_VFE_DW2_RESET_GATEWAY_TIMER (0x1 << 7)
|
||||
#define GEN6_VFE_DW2_BYPASS_GATEWAY_CONTROL (0x1 << 6)
|
||||
#define GEN6_VFE_DW2_FAST_PREEMPT (0x1 << 5)
|
||||
#define GEN7_VFE_DW2_GATEWAY_MMIO__MASK 0x00000018
|
||||
#define GEN7_VFE_DW2_GATEWAY_MMIO__SHIFT 3
|
||||
#define GEN7_VFE_DW2_GATEWAY_MMIO_NONE (0x0 << 3)
|
||||
#define GEN7_VFE_DW2_GATEWAY_MMIO_ANY (0x2 << 3)
|
||||
#define GEN7_VFE_DW2_GPGPU_MODE (0x1 << 2)
|
||||
|
||||
#define GEN75_VFE_DW3_HALF_SLICE_DISABLE__MASK 0x00000003
|
||||
#define GEN75_VFE_DW3_HALF_SLICE_DISABLE__SHIFT 0
|
||||
#define GEN75_VFE_DW3_HALF_SLICE_DISABLE_NONE 0x0
|
||||
#define GEN75_VFE_DW3_HALF_SLICE_DISABLE_23 0x1
|
||||
#define GEN75_VFE_DW3_HALF_SLICE_DISABLE_123 0x3
|
||||
|
||||
#define GEN6_VFE_DW4_URB_ENTRY_SIZE__MASK 0xffff0000
|
||||
#define GEN6_VFE_DW4_URB_ENTRY_SIZE__SHIFT 16
|
||||
#define GEN6_VFE_DW4_CURBE_SIZE__MASK 0x0000ffff
|
||||
#define GEN6_VFE_DW4_CURBE_SIZE__SHIFT 0
|
||||
|
||||
#define GEN6_VFE_DW5_SCOREBOARD_ENABLE (0x1 << 31)
|
||||
#define GEN6_VFE_DW5_SCOREBOARD_TYPE__MASK 0x40000000
|
||||
#define GEN6_VFE_DW5_SCOREBOARD_TYPE__SHIFT 30
|
||||
#define GEN6_VFE_DW5_SCOREBOARD_TYPE_STALLING (0x0 << 30)
|
||||
#define GEN6_VFE_DW5_SCOREBOARD_TYPE_NON_STALLING (0x1 << 30)
|
||||
#define GEN6_VFE_DW5_SCOREBOARD_MASK__MASK 0x000000ff
|
||||
#define GEN6_VFE_DW5_SCOREBOARD_MASK__SHIFT 0
|
||||
|
||||
#define GEN6_VFE_DW6_SCOREBOARD_3_DELTA_Y__MASK 0xf0000000
|
||||
#define GEN6_VFE_DW6_SCOREBOARD_3_DELTA_Y__SHIFT 28
|
||||
#define GEN6_VFE_DW6_SCOREBOARD_3_DELTA_X__MASK 0x0f000000
|
||||
#define GEN6_VFE_DW6_SCOREBOARD_3_DELTA_X__SHIFT 24
|
||||
#define GEN6_VFE_DW6_SCOREBOARD_2_DELTA_Y__MASK 0x00f00000
|
||||
#define GEN6_VFE_DW6_SCOREBOARD_2_DELTA_Y__SHIFT 20
|
||||
#define GEN6_VFE_DW6_SCOREBOARD_2_DELTA_X__MASK 0x000f0000
|
||||
#define GEN6_VFE_DW6_SCOREBOARD_2_DELTA_X__SHIFT 16
|
||||
#define GEN6_VFE_DW6_SCOREBOARD_1_DELTA_Y__MASK 0x0000f000
|
||||
#define GEN6_VFE_DW6_SCOREBOARD_1_DELTA_Y__SHIFT 12
|
||||
#define GEN6_VFE_DW6_SCOREBOARD_1_DELTA_X__MASK 0x00000f00
|
||||
#define GEN6_VFE_DW6_SCOREBOARD_1_DELTA_X__SHIFT 8
|
||||
#define GEN6_VFE_DW6_SCOREBOARD_0_DELTA_Y__MASK 0x000000f0
|
||||
#define GEN6_VFE_DW6_SCOREBOARD_0_DELTA_Y__SHIFT 4
|
||||
#define GEN6_VFE_DW6_SCOREBOARD_0_DELTA_X__MASK 0x0000000f
|
||||
#define GEN6_VFE_DW6_SCOREBOARD_0_DELTA_X__SHIFT 0
|
||||
|
||||
#define GEN6_VFE_DW7_SCOREBOARD_7_DELTA_Y__MASK 0xf0000000
|
||||
#define GEN6_VFE_DW7_SCOREBOARD_7_DELTA_Y__SHIFT 28
|
||||
#define GEN6_VFE_DW7_SCOREBOARD_7_DELTA_X__MASK 0x0f000000
|
||||
#define GEN6_VFE_DW7_SCOREBOARD_7_DELTA_X__SHIFT 24
|
||||
#define GEN6_VFE_DW7_SCOREBOARD_6_DELTA_Y__MASK 0x00f00000
|
||||
#define GEN6_VFE_DW7_SCOREBOARD_6_DELTA_Y__SHIFT 20
|
||||
#define GEN6_VFE_DW7_SCOREBOARD_6_DELTA_X__MASK 0x000f0000
|
||||
#define GEN6_VFE_DW7_SCOREBOARD_6_DELTA_X__SHIFT 16
|
||||
#define GEN6_VFE_DW7_SCOREBOARD_5_DELTA_Y__MASK 0x0000f000
|
||||
#define GEN6_VFE_DW7_SCOREBOARD_5_DELTA_Y__SHIFT 12
|
||||
#define GEN6_VFE_DW7_SCOREBOARD_5_DELTA_X__MASK 0x00000f00
|
||||
#define GEN6_VFE_DW7_SCOREBOARD_5_DELTA_X__SHIFT 8
|
||||
#define GEN6_VFE_DW7_SCOREBOARD_4_DELTA_Y__MASK 0x000000f0
|
||||
#define GEN6_VFE_DW7_SCOREBOARD_4_DELTA_Y__SHIFT 4
|
||||
#define GEN6_VFE_DW7_SCOREBOARD_4_DELTA_X__MASK 0x0000000f
|
||||
#define GEN6_VFE_DW7_SCOREBOARD_4_DELTA_X__SHIFT 0
|
||||
|
||||
#define GEN6_MEDIA_CURBE_LOAD__SIZE 4
|
||||
|
||||
|
||||
|
||||
#define GEN6_CURBE_LOAD_DW2_LEN__MASK 0x0001ffff
|
||||
#define GEN6_CURBE_LOAD_DW2_LEN__SHIFT 0
|
||||
|
||||
|
||||
#define GEN6_MEDIA_INTERFACE_DESCRIPTOR_LOAD__SIZE 4
|
||||
|
||||
|
||||
|
||||
#define GEN6_IDRT_LOAD_DW2_LEN__MASK 0x0001ffff
|
||||
#define GEN6_IDRT_LOAD_DW2_LEN__SHIFT 0
|
||||
|
||||
|
||||
#define GEN6_MEDIA_STATE_FLUSH__SIZE 2
|
||||
|
||||
|
||||
#define GEN6_MEDIA_FLUSH_DW1_THREAD_COUNT_WATERMARK__MASK 0x00ff0000
|
||||
#define GEN6_MEDIA_FLUSH_DW1_THREAD_COUNT_WATERMARK__SHIFT 16
|
||||
#define GEN6_MEDIA_FLUSH_DW1_BARRIER_MASK__MASK 0x0000ffff
|
||||
#define GEN6_MEDIA_FLUSH_DW1_BARRIER_MASK__SHIFT 0
|
||||
|
||||
#define GEN7_MEDIA_FLUSH_DW1_DISABLE_PREEMPTION (0x1 << 8)
|
||||
#define GEN75_MEDIA_FLUSH_DW1_FLUSH_TO_GO (0x1 << 7)
|
||||
#define GEN7_MEDIA_FLUSH_DW1_WATERMARK_REQUIRED (0x1 << 6)
|
||||
#define GEN7_MEDIA_FLUSH_DW1_IDRT_OFFSET__MASK 0x0000003f
|
||||
#define GEN7_MEDIA_FLUSH_DW1_IDRT_OFFSET__SHIFT 0
|
||||
|
||||
#define GEN7_GPGPU_WALKER__SIZE 11
|
||||
|
||||
#define GEN7_GPGPU_DW0_INDIRECT_PARAM_ENABLE (0x1 << 10)
|
||||
#define GEN7_GPGPU_DW0_PREDICATE_ENABLE (0x1 << 8)
|
||||
|
||||
#define GEN7_GPGPU_DW1_IDRT_OFFSET__MASK 0x0000003f
|
||||
#define GEN7_GPGPU_DW1_IDRT_OFFSET__SHIFT 0
|
||||
|
||||
#define GEN7_GPGPU_DW2_SIMD_SIZE__MASK 0xc0000000
|
||||
#define GEN7_GPGPU_DW2_SIMD_SIZE__SHIFT 30
|
||||
#define GEN7_GPGPU_DW2_SIMD_SIZE_SIMD8 (0x0 << 30)
|
||||
#define GEN7_GPGPU_DW2_SIMD_SIZE_SIMD16 (0x1 << 30)
|
||||
#define GEN7_GPGPU_DW2_SIMD_SIZE_SIMD32 (0x2 << 30)
|
||||
#define GEN7_GPGPU_DW2_THREAD_MAX_Z__MASK 0x003f0000
|
||||
#define GEN7_GPGPU_DW2_THREAD_MAX_Z__SHIFT 16
|
||||
#define GEN7_GPGPU_DW2_THREAD_MAX_Y__MASK 0x00003f00
|
||||
#define GEN7_GPGPU_DW2_THREAD_MAX_Y__SHIFT 8
|
||||
#define GEN7_GPGPU_DW2_THREAD_MAX_X__MASK 0x0000003f
|
||||
#define GEN7_GPGPU_DW2_THREAD_MAX_X__SHIFT 0
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#endif /* GEN_RENDER_MEDIA_XML */
|
||||
|
|
@ -271,25 +271,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
|||
#define GEN75_SCS_GREEN 0x5
|
||||
#define GEN75_SCS_BLUE 0x6
|
||||
#define GEN75_SCS_ALPHA 0x7
|
||||
#define GEN6_MOCS_LLC__MASK 0x00000003
|
||||
#define GEN6_MOCS_LLC__SHIFT 0
|
||||
#define GEN6_MOCS_LLC_PTE 0x0
|
||||
#define GEN6_MOCS_LLC_UC 0x1
|
||||
#define GEN6_MOCS_LLC_ON 0x2
|
||||
#define GEN7_MOCS_LLC__MASK 0x00000002
|
||||
#define GEN7_MOCS_LLC__SHIFT 1
|
||||
#define GEN7_MOCS_LLC_PTE (0x0 << 1)
|
||||
#define GEN7_MOCS_LLC_ON (0x1 << 1)
|
||||
#define GEN75_MOCS_LLC__MASK 0x00000006
|
||||
#define GEN75_MOCS_LLC__SHIFT 1
|
||||
#define GEN75_MOCS_LLC_PTE (0x0 << 1)
|
||||
#define GEN75_MOCS_LLC_UC (0x1 << 1)
|
||||
#define GEN75_MOCS_LLC_ON (0x2 << 1)
|
||||
#define GEN75_MOCS_LLC_ELLC (0x3 << 1)
|
||||
#define GEN7_MOCS_L3__MASK 0x00000001
|
||||
#define GEN7_MOCS_L3__SHIFT 0
|
||||
#define GEN7_MOCS_L3_UC 0x0
|
||||
#define GEN7_MOCS_L3_ON 0x1
|
||||
#define GEN6_SURFACE_STATE__SIZE 8
|
||||
|
||||
#define GEN6_SURFACE_DW0_TYPE__MASK 0xe0000000
|
||||
|
|
|
|||
|
|
@ -31,9 +31,11 @@
|
|||
#include "gen_regs.xml.h"
|
||||
#include "gen_mi.xml.h"
|
||||
#include "gen_blitter.xml.h"
|
||||
#include "gen_render.xml.h"
|
||||
#include "gen_render_surface.xml.h"
|
||||
#include "gen_render_dynamic.xml.h"
|
||||
#include "gen_render_3d.xml.h"
|
||||
#include "gen_render_media.xml.h"
|
||||
#include "gen_eu_isa.xml.h"
|
||||
#include "gen_eu_message.xml.h"
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue