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winsys/radeon: use gart_page_size instead of private size_align

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Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
This commit is contained in:
Marek Olšák 2016-05-08 13:35:19 +02:00
parent 9d8c283f28
commit bfa8a00920
3 changed files with 11 additions and 14 deletions
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20
src/gallium/winsys/radeon/drm/radeon_drm_bo.c
View file

@ -144,7 +144,7 @@ static uint64_t radeon_bomgr_find_va(struct radeon_drm_winsys *rws,
/* All VM address space holes will implicitly start aligned to the
* size alignment, so we don't need to sanitize the alignment here
*/
size = align(size, rws->size_align);
size = align(size, rws->info.gart_page_size);
pipe_mutex_lock(rws->bo_va_mutex);
/* first look for a hole */
@ -202,7 +202,7 @@ static void radeon_bomgr_free_va(struct radeon_drm_winsys *rws,
{
struct radeon_bo_va_hole *hole;
size = align(size, rws->size_align);
size = align(size, rws->info.gart_page_size);
pipe_mutex_lock(rws->bo_va_mutex);
if ((va + size) == rws->va_offset) {
@ -313,9 +313,9 @@ void radeon_bo_destroy(struct pb_buffer *_buf)
pipe_mutex_destroy(bo->map_mutex);
if (bo->initial_domain & RADEON_DOMAIN_VRAM)
rws->allocated_vram -= align(bo->base.size, rws->size_align);
rws->allocated_vram -= align(bo->base.size, rws->info.gart_page_size);
else if (bo->initial_domain & RADEON_DOMAIN_GTT)
rws->allocated_gtt -= align(bo->base.size, rws->size_align);
rws->allocated_gtt -= align(bo->base.size, rws->info.gart_page_size);
FREE(bo);
}
@ -591,9 +591,9 @@ static struct radeon_bo *radeon_create_bo(struct radeon_drm_winsys *rws,
}
if (initial_domains & RADEON_DOMAIN_VRAM)
rws->allocated_vram += align(size, rws->size_align);
rws->allocated_vram += align(size, rws->info.gart_page_size);
else if (initial_domains & RADEON_DOMAIN_GTT)
rws->allocated_gtt += align(size, rws->size_align);
rws->allocated_gtt += align(size, rws->info.gart_page_size);
return bo;
}
@ -731,7 +731,7 @@ radeon_winsys_bo_create(struct radeon_winsys *rws,
* BOs. Aligning this here helps the cached bufmgr. Especially small BOs,
* like constant/uniform buffers, can benefit from better and more reuse.
*/
size = align(size, ws->size_align);
size = align(size, ws->info.gart_page_size);
/* Only set one usage bit each for domains and flags, or the cache manager
* might consider different sets of domains / flags compatible
@ -842,7 +842,7 @@ static struct pb_buffer *radeon_winsys_bo_from_ptr(struct radeon_winsys *rws,
pipe_mutex_unlock(ws->bo_handles_mutex);
}
ws->allocated_gtt += align(bo->base.size, ws->size_align);
ws->allocated_gtt += align(bo->base.size, ws->info.gart_page_size);
return (struct pb_buffer*)bo;
}
@ -980,9 +980,9 @@ done:
bo->initial_domain = radeon_bo_get_initial_domain((void*)bo);
if (bo->initial_domain & RADEON_DOMAIN_VRAM)
ws->allocated_vram += align(bo->base.size, ws->size_align);
ws->allocated_vram += align(bo->base.size, ws->info.gart_page_size);
else if (bo->initial_domain & RADEON_DOMAIN_GTT)
ws->allocated_gtt += align(bo->base.size, ws->size_align);
ws->allocated_gtt += align(bo->base.size, ws->info.gart_page_size);
return (struct pb_buffer*)bo;

2
src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
View file

@ -834,7 +834,7 @@ radeon_drm_winsys_create(int fd, radeon_screen_create_t screen_create)
list_inithead(&ws->va_holes);
/* TTM aligns the BO size to the CPU page size */
ws->size_align = sysconf(_SC_PAGESIZE);
ws->info.gart_page_size = sysconf(_SC_PAGESIZE);
ws->ncs = 0;
pipe_semaphore_init(&ws->cs_queued, 0);

3
src/gallium/winsys/radeon/drm/radeon_drm_winsys.h
View file

@ -92,9 +92,6 @@ struct radeon_drm_winsys {
uint64_t va_offset;
struct list_head va_holes;
/* BO size alignment */
unsigned size_align;
struct radeon_surface_manager *surf_man;
uint32_t num_cpus; /* Number of CPUs. */