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i965/shader: Get rid of the shader, prog, and shader_prog fields

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Unfortunately, we can't get rid of them entirely.  The FS backend still
needs gl_program for handling TEXTURE_RECTANGLE.  The GS vec4 backend still
needs gl_shader_program for handling transfom feedback.  However, the VS
needs neither and we can substantially reduce the amount they are used.
One day we will be free from their tyranny.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
This commit is contained in:
Jason Ekstrand 2015-10-01 15:21:57 -07:00
parent 404419ee1a
commit bf7b6fd3fd
19 changed files with 68 additions and 99 deletions
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21
src/mesa/drivers/dri/i965/brw_fs.cpp
View file

@ -5060,7 +5060,6 @@ bool
fs_visitor::run_cs()
{
assert(stage == MESA_SHADER_COMPUTE);
assert(shader);
setup_cs_payload();
@ -5116,9 +5115,8 @@ brw_wm_fs_emit(struct brw_context *brw,
/* Now the main event: Visit the shader IR and generate our FS IR for it.
*/
fs_visitor v(brw->intelScreen->compiler, brw,
mem_ctx, MESA_SHADER_FRAGMENT, key, &prog_data->base,
prog, &fp->Base, 8, st_index8);
fs_visitor v(brw->intelScreen->compiler, brw, mem_ctx, key,
&prog_data->base, &fp->Base, fp->Base.nir, 8, st_index8);
if (!v.run_fs(false /* do_rep_send */)) {
if (prog) {
prog->LinkStatus = false;
@ -5132,9 +5130,8 @@ brw_wm_fs_emit(struct brw_context *brw,
}
cfg_t *simd16_cfg = NULL;
fs_visitor v2(brw->intelScreen->compiler, brw,
mem_ctx, MESA_SHADER_FRAGMENT, key, &prog_data->base,
prog, &fp->Base, 16, st_index16);
fs_visitor v2(brw->intelScreen->compiler, brw, mem_ctx, key,
&prog_data->base, &fp->Base, fp->Base.nir, 16, st_index16);
if (likely(!(INTEL_DEBUG & DEBUG_NO16) || brw->use_rep_send)) {
if (!v.simd16_unsupported) {
/* Try a SIMD16 compile */
@ -5248,9 +5245,8 @@ brw_cs_emit(struct brw_context *brw,
/* Now the main event: Visit the shader IR and generate our CS IR for it.
*/
fs_visitor v8(brw->intelScreen->compiler, brw,
mem_ctx, MESA_SHADER_COMPUTE, key, &prog_data->base, prog,
&cp->Base, 8, st_index);
fs_visitor v8(brw->intelScreen->compiler, brw, mem_ctx, key,
&prog_data->base, &cp->Base, cp->Base.nir, 8, st_index);
if (!v8.run_cs()) {
fail_msg = v8.fail_msg;
} else if (local_workgroup_size <= 8 * brw->max_cs_threads) {
@ -5258,9 +5254,8 @@ brw_cs_emit(struct brw_context *brw,
prog_data->simd_size = 8;
}
fs_visitor v16(brw->intelScreen->compiler, brw,
mem_ctx, MESA_SHADER_COMPUTE, key, &prog_data->base, prog,
&cp->Base, 16, st_index);
fs_visitor v16(brw->intelScreen->compiler, brw, mem_ctx, key,
&prog_data->base, &cp->Base, cp->Base.nir, 16, st_index);
if (likely(!(INTEL_DEBUG & DEBUG_NO16)) &&
!fail_msg && !v8.simd16_unsupported &&
local_workgroup_size <= 16 * brw->max_cs_threads) {

4
src/mesa/drivers/dri/i965/brw_fs.h
View file

@ -93,11 +93,10 @@ class fs_visitor : public backend_shader
public:
fs_visitor(const struct brw_compiler *compiler, void *log_data,
void *mem_ctx,
gl_shader_stage stage,
const void *key,
struct brw_stage_prog_data *prog_data,
struct gl_shader_program *shader_prog,
struct gl_program *prog,
nir_shader *shader,
unsigned dispatch_width,
int shader_time_index);
@ -300,6 +299,7 @@ public:
const struct brw_sampler_prog_key_data *key_tex;
struct brw_stage_prog_data *prog_data;
struct gl_program *prog;
int *param_size;

2
src/mesa/drivers/dri/i965/brw_fs_nir.cpp
View file

@ -1813,8 +1813,6 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
unsigned ubo_index = const_uniform_block ? const_uniform_block->u[0] : 0;
int reg_width = dispatch_width / 8;
assert(shader->base.UniformBlocks[ubo_index].IsShaderStorage);
/* Set LOD = 0 */
fs_reg source = fs_reg(0);

8
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
View file

@ -1066,16 +1066,14 @@ fs_visitor::emit_barrier()
fs_visitor::fs_visitor(const struct brw_compiler *compiler, void *log_data,
void *mem_ctx,
gl_shader_stage stage,
const void *key,
struct brw_stage_prog_data *prog_data,
struct gl_shader_program *shader_prog,
struct gl_program *prog,
nir_shader *shader,
unsigned dispatch_width,
int shader_time_index)
: backend_shader(compiler, log_data, mem_ctx,
shader_prog, prog, prog_data, stage),
key(key), prog_data(prog_data),
: backend_shader(compiler, log_data, mem_ctx, shader, prog_data),
key(key), prog_data(prog_data), prog(prog),
dispatch_width(dispatch_width),
shader_time_index(shader_time_index),
promoted_constants(0),

14
src/mesa/drivers/dri/i965/brw_shader.cpp
View file

@ -895,22 +895,16 @@ brw_abs_immediate(enum brw_reg_type type, struct brw_reg *reg)
backend_shader::backend_shader(const struct brw_compiler *compiler,
void *log_data,
void *mem_ctx,
struct gl_shader_program *shader_prog,
struct gl_program *prog,
struct brw_stage_prog_data *stage_prog_data,
gl_shader_stage stage)
nir_shader *shader,
struct brw_stage_prog_data *stage_prog_data)
: compiler(compiler),
log_data(log_data),
devinfo(compiler->devinfo),
nir(prog->nir),
shader(shader_prog ?
(struct brw_shader *)shader_prog->_LinkedShaders[stage] : NULL),
shader_prog(shader_prog),
prog(prog),
nir(shader),
stage_prog_data(stage_prog_data),
mem_ctx(mem_ctx),
cfg(NULL),
stage(stage)
stage(shader->stage)
{
debug_enabled = INTEL_DEBUG & intel_debug_flag_for_shader_stage(stage);
stage_name = _mesa_shader_stage_to_string(stage);

9
src/mesa/drivers/dri/i965/brw_shader.h
View file

@ -225,10 +225,8 @@ protected:
backend_shader(const struct brw_compiler *compiler,
void *log_data,
void *mem_ctx,
struct gl_shader_program *shader_prog,
struct gl_program *prog,
struct brw_stage_prog_data *stage_prog_data,
gl_shader_stage stage);
nir_shader *shader,
struct brw_stage_prog_data *stage_prog_data);
public:
@ -237,9 +235,6 @@ public:
const struct brw_device_info * const devinfo;
nir_shader *nir;
struct brw_shader * const shader;
struct gl_shader_program * const shader_prog;
struct gl_program * const prog;
struct brw_stage_prog_data * const stage_prog_data;
/** ralloc context for temporary data used during compile */

9
src/mesa/drivers/dri/i965/brw_vec4.cpp
View file

@ -1807,7 +1807,6 @@ vec4_visitor::run()
emit_prolog();
assert(prog->nir != NULL);
emit_nir_code();
if (failed)
return false;
@ -1962,9 +1961,9 @@ brw_vs_emit(struct brw_context *brw,
prog_data->base.dispatch_mode = DISPATCH_MODE_SIMD8;
fs_visitor v(brw->intelScreen->compiler, brw,
mem_ctx, MESA_SHADER_VERTEX, key,
&prog_data->base.base, prog, &vp->Base,
8, st_index);
mem_ctx, key, &prog_data->base.base,
NULL, /* prog; Only used for TEXTURE_RECTANGLE on gen < 8 */
vp->Base.nir, 8, st_index);
if (!v.run_vs(brw_select_clip_planes(&brw->ctx))) {
if (prog) {
prog->LinkStatus = false;
@ -2001,7 +2000,7 @@ brw_vs_emit(struct brw_context *brw,
prog_data->base.dispatch_mode = DISPATCH_MODE_4X2_DUAL_OBJECT;
vec4_vs_visitor v(brw->intelScreen->compiler, brw, key, prog_data,
vp, prog, brw_select_clip_planes(&brw->ctx),
vp->Base.nir, brw_select_clip_planes(&brw->ctx),
mem_ctx, st_index,
!_mesa_is_gles3(&brw->ctx));
if (!v.run()) {

4
src/mesa/drivers/dri/i965/brw_vec4.h
View file

@ -70,11 +70,9 @@ class vec4_visitor : public backend_shader
public:
vec4_visitor(const struct brw_compiler *compiler,
void *log_data,
struct gl_program *prog,
const struct brw_sampler_prog_key_data *key,
struct brw_vue_prog_data *prog_data,
struct gl_shader_program *shader_prog,
gl_shader_stage stage,
nir_shader *shader,
void *mem_ctx,
bool no_spills,
int shader_time_index);

24
src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp
View file

@ -38,13 +38,14 @@ vec4_gs_visitor::vec4_gs_visitor(const struct brw_compiler *compiler,
void *log_data,
struct brw_gs_compile *c,
struct gl_shader_program *prog,
nir_shader *shader,
void *mem_ctx,
bool no_spills,
int shader_time_index)
: vec4_visitor(compiler, log_data,
&c->gp->program.Base, &c->key.tex,
&c->prog_data.base, prog, MESA_SHADER_GEOMETRY, mem_ctx,
: vec4_visitor(compiler, log_data, &c->key.tex,
&c->prog_data.base, shader, mem_ctx,
no_spills, shader_time_index),
shader_prog(prog),
c(c)
{
}
@ -621,12 +622,10 @@ brw_gs_emit(struct brw_context *brw,
void *mem_ctx,
unsigned *final_assembly_size)
{
if (unlikely(INTEL_DEBUG & DEBUG_GS)) {
struct brw_shader *shader =
(brw_shader *) prog->_LinkedShaders[MESA_SHADER_GEOMETRY];
struct gl_shader *shader = prog->_LinkedShaders[MESA_SHADER_GEOMETRY];
brw_dump_ir("geometry", prog, &shader->base, NULL);
}
if (unlikely(INTEL_DEBUG & DEBUG_GS))
brw_dump_ir("geometry", prog, shader, NULL);
int st_index = -1;
if (INTEL_DEBUG & DEBUG_SHADER_TIME)
@ -642,7 +641,8 @@ brw_gs_emit(struct brw_context *brw,
c->prog_data.base.dispatch_mode = DISPATCH_MODE_4X2_DUAL_OBJECT;
vec4_gs_visitor v(brw->intelScreen->compiler, brw,
c, prog, mem_ctx, true /* no_spills */, st_index);
c, prog, shader->Program->nir,
mem_ctx, true /* no_spills */, st_index);
if (v.run()) {
return generate_assembly(brw, prog, &c->gp->program.Base,
&c->prog_data.base, mem_ctx, v.cfg,
@ -684,11 +684,13 @@ brw_gs_emit(struct brw_context *brw,
if (brw->gen >= 7)
gs = new vec4_gs_visitor(brw->intelScreen->compiler, brw,
c, prog, mem_ctx, false /* no_spills */,
c, prog, shader->Program->nir,
mem_ctx, false /* no_spills */,
st_index);
else
gs = new gen6_gs_visitor(brw->intelScreen->compiler, brw,
c, prog, mem_ctx, false /* no_spills */,
c, prog, shader->Program->nir,
mem_ctx, false /* no_spills */,
st_index);
if (!gs->run()) {

3
src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.h
View file

@ -71,6 +71,7 @@ public:
void *log_data,
struct brw_gs_compile *c,
struct gl_shader_program *prog,
nir_shader *shader,
void *mem_ctx,
bool no_spills,
int shader_time_index);
@ -96,6 +97,8 @@ protected:
void emit_control_data_bits();
void set_stream_control_data_bits(unsigned stream_id);
struct gl_shader_program *shader_prog;
src_reg vertex_count;
src_reg control_data_bits;
const struct brw_gs_compile * const c;

2
src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
View file

@ -425,8 +425,6 @@ vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
nir_const_value *const_uniform_block = nir_src_as_const_value(instr->src[0]);
unsigned ubo_index = const_uniform_block ? const_uniform_block->u[0] : 0;
assert(shader->base.UniformBlocks[ubo_index].IsShaderStorage);
src_reg surf_index = src_reg(prog_data->base.binding_table.ubo_start +
ubo_index);
dst_reg result_dst = get_nir_dest(instr->dest);

7
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
View file

@ -1824,16 +1824,13 @@ vec4_visitor::resolve_ud_negate(src_reg *reg)
vec4_visitor::vec4_visitor(const struct brw_compiler *compiler,
void *log_data,
struct gl_program *prog,
const struct brw_sampler_prog_key_data *key_tex,
struct brw_vue_prog_data *prog_data,
struct gl_shader_program *shader_prog,
gl_shader_stage stage,
nir_shader *shader,
void *mem_ctx,
bool no_spills,
int shader_time_index)
: backend_shader(compiler, log_data, mem_ctx,
shader_prog, prog, &prog_data->base, stage),
: backend_shader(compiler, log_data, mem_ctx, shader, &prog_data->base),
key_tex(key_tex),
prog_data(prog_data),
fail_msg(NULL),

11
src/mesa/drivers/dri/i965/brw_vec4_vs_visitor.cpp
View file

@ -301,20 +301,15 @@ vec4_vs_visitor::vec4_vs_visitor(const struct brw_compiler *compiler,
void *log_data,
const struct brw_vs_prog_key *key,
struct brw_vs_prog_data *vs_prog_data,
struct gl_vertex_program *vp,
struct gl_shader_program *prog,
nir_shader *shader,
gl_clip_plane *clip_planes,
void *mem_ctx,
int shader_time_index,
bool use_legacy_snorm_formula)
: vec4_visitor(compiler, log_data,
&vp->Base, &key->tex, &vs_prog_data->base, prog,
MESA_SHADER_VERTEX,
mem_ctx, false /* no_spills */,
shader_time_index),
: vec4_visitor(compiler, log_data, &key->tex, &vs_prog_data->base, shader,
mem_ctx, false /* no_spills */, shader_time_index),
key(key),
vs_prog_data(vs_prog_data),
vp(vp),
clip_planes(clip_planes),
use_legacy_snorm_formula(use_legacy_snorm_formula)
{

4
src/mesa/drivers/dri/i965/brw_vs.h
View file

@ -87,8 +87,7 @@ public:
void *log_data,
const struct brw_vs_prog_key *key,
struct brw_vs_prog_data *vs_prog_data,
struct gl_vertex_program *vp,
struct gl_shader_program *prog,
nir_shader *shader,
gl_clip_plane *clip_planes,
void *mem_ctx,
int shader_time_index,
@ -114,7 +113,6 @@ private:
const struct brw_vs_prog_key *const key;
struct brw_vs_prog_data * const vs_prog_data;
struct gl_vertex_program *const vp;
src_reg *vp_temp_regs;
src_reg vp_addr_reg;

3
src/mesa/drivers/dri/i965/gen6_gs_visitor.h
View file

@ -39,10 +39,11 @@ public:
void *log_data,
struct brw_gs_compile *c,
struct gl_shader_program *prog,
nir_shader *shader,
void *mem_ctx,
bool no_spills,
int shader_time_index) :
vec4_gs_visitor(comp, log_data, c, prog, mem_ctx, no_spills,
vec4_gs_visitor(comp, log_data, c, prog, shader, mem_ctx, no_spills,
shader_time_index) {}
protected:

12
src/mesa/drivers/dri/i965/test_fs_cmod_propagation.cpp
View file

@ -46,10 +46,10 @@ class cmod_propagation_fs_visitor : public fs_visitor
public:
cmod_propagation_fs_visitor(struct brw_compiler *compiler,
struct brw_wm_prog_data *prog_data,
struct gl_shader_program *shader_prog)
: fs_visitor(compiler, NULL, NULL, MESA_SHADER_FRAGMENT, NULL,
&prog_data->base, shader_prog,
(struct gl_program *) NULL, 8, -1) {}
nir_shader *shader)
: fs_visitor(compiler, NULL, NULL, NULL,
&prog_data->base, (struct gl_program *) NULL,
shader, 8, -1) {}
};
@ -62,9 +62,9 @@ void cmod_propagation_test::SetUp()
fp = ralloc(NULL, struct brw_fragment_program);
prog_data = ralloc(NULL, struct brw_wm_prog_data);
shader_prog = ralloc(NULL, struct gl_shader_program);
nir_shader *shader = nir_shader_create(NULL, MESA_SHADER_FRAGMENT, NULL);
v = new cmod_propagation_fs_visitor(compiler, prog_data, shader_prog);
v = new cmod_propagation_fs_visitor(compiler, prog_data, shader);
_mesa_init_fragment_program(ctx, &fp->program, GL_FRAGMENT_SHADER, 0);

12
src/mesa/drivers/dri/i965/test_fs_saturate_propagation.cpp
View file

@ -46,10 +46,10 @@ class saturate_propagation_fs_visitor : public fs_visitor
public:
saturate_propagation_fs_visitor(struct brw_compiler *compiler,
struct brw_wm_prog_data *prog_data,
struct gl_shader_program *shader_prog)
: fs_visitor(compiler, NULL, NULL, MESA_SHADER_FRAGMENT, NULL,
&prog_data->base, shader_prog,
(struct gl_program *) NULL, 8, -1) {}
nir_shader *shader)
: fs_visitor(compiler, NULL, NULL, NULL,
&prog_data->base, (struct gl_program *) NULL,
shader, 8, -1) {}
};
@ -62,9 +62,9 @@ void saturate_propagation_test::SetUp()
fp = ralloc(NULL, struct brw_fragment_program);
prog_data = ralloc(NULL, struct brw_wm_prog_data);
shader_prog = ralloc(NULL, struct gl_shader_program);
nir_shader *shader = nir_shader_create(NULL, MESA_SHADER_FRAGMENT, NULL);
v = new saturate_propagation_fs_visitor(compiler, prog_data, shader_prog);
v = new saturate_propagation_fs_visitor(compiler, prog_data, shader);
_mesa_init_fragment_program(ctx, &fp->program, GL_FRAGMENT_SHADER, 0);

9
src/mesa/drivers/dri/i965/test_vec4_copy_propagation.cpp
View file

@ -45,9 +45,8 @@ class copy_propagation_vec4_visitor : public vec4_visitor
{
public:
copy_propagation_vec4_visitor(struct brw_compiler *compiler,
struct gl_shader_program *shader_prog)
: vec4_visitor(compiler, NULL, NULL, NULL, NULL, shader_prog,
MESA_SHADER_VERTEX, NULL,
nir_shader *shader)
: vec4_visitor(compiler, NULL, NULL, NULL, shader, NULL,
false /* no_spills */, -1)
{
}
@ -95,9 +94,9 @@ void copy_propagation_test::SetUp()
vp = ralloc(NULL, struct brw_vertex_program);
shader_prog = ralloc(NULL, struct gl_shader_program);
nir_shader *shader = nir_shader_create(NULL, MESA_SHADER_VERTEX, NULL);
v = new copy_propagation_vec4_visitor(compiler, shader_prog);
v = new copy_propagation_vec4_visitor(compiler, shader);
_mesa_init_vertex_program(ctx, &vp->program, GL_VERTEX_SHADER, 0);

9
src/mesa/drivers/dri/i965/test_vec4_register_coalesce.cpp
View file

@ -48,9 +48,8 @@ class register_coalesce_vec4_visitor : public vec4_visitor
{
public:
register_coalesce_vec4_visitor(struct brw_compiler *compiler,
struct gl_shader_program *shader_prog)
: vec4_visitor(compiler, NULL, NULL, NULL, NULL, shader_prog,
MESA_SHADER_VERTEX, NULL,
nir_shader *shader)
: vec4_visitor(compiler, NULL, NULL, NULL, shader, NULL,
false /* no_spills */, -1)
{
}
@ -98,9 +97,9 @@ void register_coalesce_test::SetUp()
vp = ralloc(NULL, struct brw_vertex_program);
shader_prog = ralloc(NULL, struct gl_shader_program);
nir_shader *shader = nir_shader_create(NULL, MESA_SHADER_VERTEX, NULL);
v = new register_coalesce_vec4_visitor(compiler, shader_prog);
v = new register_coalesce_vec4_visitor(compiler, shader);
_mesa_init_vertex_program(ctx, &vp->program, GL_VERTEX_SHADER, 0);