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freedreno/ir3: fix immediate usage in tgsi tex fe

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get_immediate will return a const reference, the requested immediate
isn't necessarily in the x slot. Make sure to use the swizzle.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit 3e7bc67285)
This commit is contained in:
Ilia Mirkin 2015-04-27 23:47:40 -04:00 • committed by Emil Velikov
parent e4f74121db
commit bf33fc653d
1 changed files with 9 additions and 5 deletions
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14
src/gallium/drivers/freedreno/ir3/ir3_compiler.c
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@ -1615,7 +1615,7 @@ trans_samp(const struct instr_translater *t,
instr->cat1.src_type = type_mov; instr->cat1.src_type = type_mov;
instr->cat1.dst_type = type_mov; instr->cat1.dst_type = type_mov;
add_dst_reg(ctx, instr, &tmp_dst, i); add_dst_reg(ctx, instr, &tmp_dst, i);
add_src_reg(ctx, instr, &zero, 0); add_src_reg(ctx, instr, &zero, zero.SwizzleX);
i++; i++;
} }
if (tgt->array) { if (tgt->array) {
@ -1669,15 +1669,18 @@ trans_samp(const struct instr_translater *t,
*/ */
if (inst->Instruction.Opcode == TGSI_OPCODE_TXD) { if (inst->Instruction.Opcode == TGSI_OPCODE_TXD) {
while (collect->regs_count < 5) while (collect->regs_count < 5)
ssa_src(ctx, ir3_reg_create(collect, 0, IR3_REG_SSA), &zero, 0); ssa_src(ctx, ir3_reg_create(collect, 0, IR3_REG_SSA),
&zero, zero.SwizzleX);
for (i = 0; i < tgt->dims; i++) for (i = 0; i < tgt->dims; i++)
ssa_src(ctx, ir3_reg_create(collect, 0, IR3_REG_SSA), dpdx, i); ssa_src(ctx, ir3_reg_create(collect, 0, IR3_REG_SSA), dpdx, i);
if (tgt->dims < 2) if (tgt->dims < 2)
ssa_src(ctx, ir3_reg_create(collect, 0, IR3_REG_SSA), &zero, 0); ssa_src(ctx, ir3_reg_create(collect, 0, IR3_REG_SSA),
&zero, zero.SwizzleX);
for (i = 0; i < tgt->dims; i++) for (i = 0; i < tgt->dims; i++)
ssa_src(ctx, ir3_reg_create(collect, 0, IR3_REG_SSA), dpdy, i); ssa_src(ctx, ir3_reg_create(collect, 0, IR3_REG_SSA), dpdy, i);
if (tgt->dims < 2) if (tgt->dims < 2)
ssa_src(ctx, ir3_reg_create(collect, 0, IR3_REG_SSA), &zero, 0); ssa_src(ctx, ir3_reg_create(collect, 0, IR3_REG_SSA),
&zero, zero.SwizzleX);
tinf.src_wrmask |= ((1 << (2 * MAX2(tgt->dims, 2))) - 1) << 4; tinf.src_wrmask |= ((1 << (2 * MAX2(tgt->dims, 2))) - 1) << 4;
} }
@ -1700,7 +1703,8 @@ trans_samp(const struct instr_translater *t,
ssa_src(ctx, ir3_reg_create(collect, 0, IR3_REG_SSA), ssa_src(ctx, ir3_reg_create(collect, 0, IR3_REG_SSA),
offset, i); offset, i);
if (tgt->dims < 2) if (tgt->dims < 2)
ssa_src(ctx, ir3_reg_create(collect, 0, IR3_REG_SSA), &zero, 0); ssa_src(ctx, ir3_reg_create(collect, 0, IR3_REG_SSA),
&zero, zero.SwizzleX);
} }
if (inst->Instruction.Opcode == TGSI_OPCODE_TXB2) if (inst->Instruction.Opcode == TGSI_OPCODE_TXB2)
ssa_src(ctx, ir3_reg_create(collect, 0, IR3_REG_SSA), ssa_src(ctx, ir3_reg_create(collect, 0, IR3_REG_SSA),