diff --git a/src/amd/vulkan/nir/radv_nir.h b/src/amd/vulkan/nir/radv_nir.h
index 68fbba360bf..62e310db857 100644
--- a/src/amd/vulkan/nir/radv_nir.h
+++ b/src/amd/vulkan/nir/radv_nir.h
@@ -26,7 +26,7 @@ struct radv_shader_layout;
 struct radv_device;
 struct radv_graphics_state_key;
 
-void radv_nir_apply_pipeline_layout(nir_shader *shader, struct radv_device *device,
+bool radv_nir_apply_pipeline_layout(nir_shader *shader, struct radv_device *device,
                                     const struct radv_shader_stage *stage);
 
 bool radv_nir_lower_abi(nir_shader *shader, enum amd_gfx_level gfx_level, const struct radv_shader_stage *stage,
diff --git a/src/amd/vulkan/nir/radv_nir_apply_pipeline_layout.c b/src/amd/vulkan/nir/radv_nir_apply_pipeline_layout.c
index 703b8b51f30..2b6744b4c05 100644
--- a/src/amd/vulkan/nir/radv_nir_apply_pipeline_layout.c
+++ b/src/amd/vulkan/nir/radv_nir_apply_pipeline_layout.c
@@ -409,7 +409,7 @@ load_push_constant(nir_builder *b, apply_layout_state *state, nir_intrinsic_inst
    return nir_extract_bits(b, data, num_loads, 0, intrin->def.num_components, bit_size);
 }
 
-static void
+static bool
 apply_layout_to_intrin(nir_builder *b, apply_layout_state *state, nir_intrinsic_instr *intrin)
 {
    b->cursor = nir_before_instr(&intrin->instr);
@@ -454,11 +454,13 @@ apply_layout_to_intrin(nir_builder *b, apply_layout_state *state, nir_intrinsic_
       break;
    }
    default:
-      break;
+      return false;
    }
+
+   return true;
 }
 
-static void
+static bool
 apply_layout_to_tex(nir_builder *b, apply_layout_state *state, nir_tex_instr *tex)
 {
    b->cursor = nir_before_instr(&tex->instr);
@@ -526,7 +528,7 @@ apply_layout_to_tex(nir_builder *b, apply_layout_state *state, nir_tex_instr *te
 
    if (tex->op == nir_texop_descriptor_amd) {
       nir_def_replace(&tex->def, image);
-      return;
+      return true;
    }
 
    for (unsigned i = 0; i < tex->num_srcs; i++) {
@@ -543,11 +545,14 @@ apply_layout_to_tex(nir_builder *b, apply_layout_state *state, nir_tex_instr *te
          break;
       }
    }
+
+   return true;
 }
 
-void
+bool
 radv_nir_apply_pipeline_layout(nir_shader *shader, struct radv_device *device, const struct radv_shader_stage *stage)
 {
+   bool progress = false;
    const struct radv_physical_device *pdev = radv_device_physical(device);
    const struct radv_instance *instance = radv_physical_device_instance(pdev);
 
@@ -577,12 +582,18 @@ radv_nir_apply_pipeline_layout(nir_shader *shader, struct radv_device *device, c
       nir_foreach_block_reverse (block, function->impl) {
          nir_foreach_instr_reverse_safe (instr, block) {
             if (instr->type == nir_instr_type_tex)
-               apply_layout_to_tex(&b, &state, nir_instr_as_tex(instr));
+               progress |= apply_layout_to_tex(&b, &state, nir_instr_as_tex(instr));
             else if (instr->type == nir_instr_type_intrinsic)
-               apply_layout_to_intrin(&b, &state, nir_instr_as_intrinsic(instr));
+               progress |= apply_layout_to_intrin(&b, &state, nir_instr_as_intrinsic(instr));
          }
       }
-
-      nir_metadata_preserve(function->impl, nir_metadata_control_flow);
    }
+
+   if (progress) {
+      nir_foreach_function (function, shader) {
+         nir_metadata_preserve(function->impl, nir_metadata_control_flow);
+      }
+   }
+
+   return progress;
 }
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 5a361245ac9..91a8625ee31 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -398,7 +398,7 @@ radv_postprocess_nir(struct radv_device *device, const struct radv_graphics_stat
       NIR_PASS(_, stage->nir, nir_opt_constant_folding);
 
    /* TODO: vectorize loads after this to vectorize loading adjacent descriptors */
-   NIR_PASS_V(stage->nir, radv_nir_apply_pipeline_layout, device, stage);
+   NIR_PASS(_, stage->nir, radv_nir_apply_pipeline_layout, device, stage);
 
    NIR_PASS(_, stage->nir, nir_lower_alu_width, opt_vectorize_callback, device);