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i965: Program DWord Length in MI_FLUSH_DW

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Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Cc: <mesa-stable@lists.freedesktop.org>
(cherry picked from commit 6165fda59b)

Squashed with:

i965: Remove DWord length from MI_FLUSH_DW definition

Fixes: 6165fda59b ("i965: Program DWord Length in MI_FLUSH_DW")
Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
(cherry picked from commit 822fd2341d)
This commit is contained in:
Anuj Phogat 2017-11-10 14:39:17 -08:00 • committed by Emil Velikov
parent d38e92b6e9
commit bf0c7200bd
3 changed files with 3 additions and 3 deletions
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2
src/mesa/drivers/dri/i965/brw_defines.h
View file

@ -1428,7 +1428,7 @@ enum brw_pixel_shader_coverage_mask_mode {
#define MI_LOAD_REGISTER_IMM (CMD_MI | (0x22 << 23))
#define MI_LOAD_REGISTER_REG (CMD_MI | (0x2A << 23))
#define MI_FLUSH_DW (CMD_MI | (0x26 << 23) | 2)
#define MI_FLUSH_DW (CMD_MI | (0x26 << 23))
#define MI_STORE_REGISTER_MEM (CMD_MI | (0x24 << 23))
# define MI_STORE_REGISTER_MEM_USE_GGTT (1 << 22)

2
src/mesa/drivers/dri/i965/brw_pipe_control.c
View file

@ -464,7 +464,7 @@ brw_emit_mi_flush(struct brw_context *brw)
if (brw->batch.ring == BLT_RING && devinfo->gen >= 6) {
BEGIN_BATCH_BLT(4);
OUT_BATCH(MI_FLUSH_DW);
OUT_BATCH(MI_FLUSH_DW | (4 - 2));
OUT_BATCH(0);
OUT_BATCH(0);
OUT_BATCH(0);

2
src/mesa/drivers/dri/i965/intel_blit.c
View file

@ -106,7 +106,7 @@ set_blitter_tiling(struct brw_context *brw,
assert(devinfo->gen >= 6);
/* Idle the blitter before we update how tiling is interpreted. */
OUT_BATCH(MI_FLUSH_DW);
OUT_BATCH(MI_FLUSH_DW | (4 - 2));
OUT_BATCH(0);
OUT_BATCH(0);
OUT_BATCH(0);