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radv: fix initializing the HTILE buffer on transfer queue

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When only of the depth/stencil aspects is used, RADV dispatches a
compute shader to initialize the HTILE buffer. But dispatching on SDMA
just hangs and the only way to initialize the HTILE buffer is to clear
both aspects using a memory fill operation.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31803>
This commit is contained in:
Samuel Pitoiset 2024-10-23 16:16:46 +02:00 • committed by Marge Bot
parent dcb88ea4ab
commit be81c8b8db
1 changed files with 10 additions and 2 deletions
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12
src/amd/vulkan/meta/radv_meta_clear.c
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@ -806,8 +806,9 @@ radv_get_htile_fast_clear_value(const struct radv_device *device, const struct r
}
static uint32_t
radv_get_htile_mask(const struct radv_device *device, const struct radv_image *image, VkImageAspectFlags aspects)
radv_get_htile_mask(struct radv_cmd_buffer *cmd_buffer, const struct radv_image *image, VkImageAspectFlags aspects)
{
const struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
uint32_t mask = 0;
if (radv_image_tile_stencil_disabled(device, image)) {
@ -818,6 +819,13 @@ radv_get_htile_mask(const struct radv_device *device, const struct radv_image *i
mask |= 0xfffffc0f;
if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
mask |= 0x000003f0;
if (cmd_buffer->qf == RADV_QUEUE_TRANSFER) {
/* Clear both aspects on SDMA, it's not ideal but there is no other way to initialize the
* HTILE buffer.
*/
mask = UINT32_MAX;
}
}
return mask;
@ -1342,7 +1350,7 @@ radv_clear_htile(struct radv_cmd_buffer *cmd_buffer, const struct radv_image *im
uint32_t flush_bits = 0;
uint32_t htile_mask;
htile_mask = radv_get_htile_mask(device, image, range->aspectMask);
htile_mask = radv_get_htile_mask(cmd_buffer, image, range->aspectMask);
if (level_count != image->vk.mip_levels) {
assert(pdev->info.gfx_level >= GFX10);