From be6bdb09182ae53bab28b11bc7219890cdea77b2 Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Mon, 9 Aug 2021 21:57:41 +0200 Subject: [PATCH] radv: fix copying depth+stencil images on compute Using separate aspects is required. Fixes few CTS failures (dEQP-VK.api.copy_and_blit.*) when the compute path is forced in the driver. Note that CTS coverage of compute queue is rather limited. Cc: 21.2 mesa-stable Signed-off-by: Samuel Pitoiset Reviewed-by: Bas Nieuwenhuizen Part-of: --- src/amd/vulkan/radv_meta_bufimage.c | 59 ++++++++++++++++++----------- 1 file changed, 36 insertions(+), 23 deletions(-) diff --git a/src/amd/vulkan/radv_meta_bufimage.c b/src/amd/vulkan/radv_meta_bufimage.c index ea3bec3323a..ef3ccde1065 100644 --- a/src/amd/vulkan/radv_meta_bufimage.c +++ b/src/amd/vulkan/radv_meta_bufimage.c @@ -1288,18 +1288,22 @@ fail_itob: static void create_iview(struct radv_cmd_buffer *cmd_buffer, struct radv_meta_blit2d_surf *surf, - struct radv_image_view *iview) + struct radv_image_view *iview, VkFormat format, VkImageAspectFlagBits aspects) { VkImageViewType view_type = cmd_buffer->device->physical_device->rad_info.chip_class < GFX9 ? VK_IMAGE_VIEW_TYPE_2D : radv_meta_get_view_type(surf->image); + + if (format == VK_FORMAT_UNDEFINED) + format = surf->format; + radv_image_view_init(iview, cmd_buffer->device, &(VkImageViewCreateInfo){ .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO, .image = radv_image_to_handle(surf->image), .viewType = view_type, - .format = surf->format, - .subresourceRange = {.aspectMask = surf->aspect_mask, + .format = format, + .subresourceRange = {.aspectMask = aspects, .baseMipLevel = surf->level, .levelCount = 1, .baseArrayLayer = surf->layer, @@ -1440,7 +1444,7 @@ radv_meta_image_to_buffer(struct radv_cmd_buffer *cmd_buffer, struct radv_meta_b struct radv_image_view src_view; struct radv_buffer_view dst_view; - create_iview(cmd_buffer, src, &src_view); + create_iview(cmd_buffer, src, &src_view, VK_FORMAT_UNDEFINED, src->aspect_mask); create_bview(cmd_buffer, dst->buffer, dst->offset, dst->format, &dst_view); itob_bind_descriptors(cmd_buffer, &src_view, &dst_view); @@ -1586,7 +1590,7 @@ radv_meta_buffer_to_image_cs(struct radv_cmd_buffer *cmd_buffer, } create_bview(cmd_buffer, src->buffer, src->offset, src->format, &src_view); - create_iview(cmd_buffer, dst, &dst_view); + create_iview(cmd_buffer, dst, &dst_view, VK_FORMAT_UNDEFINED, dst->aspect_mask); btoi_bind_descriptors(cmd_buffer, &src_view, &dst_view); if (device->physical_device->rad_info.chip_class >= GFX9 && dst->image->type == VK_IMAGE_TYPE_3D) @@ -1741,27 +1745,36 @@ radv_meta_image_to_image_cs(struct radv_cmd_buffer *cmd_buffer, struct radv_meta return; } - create_iview(cmd_buffer, src, &src_view); - create_iview(cmd_buffer, dst, &dst_view); + u_foreach_bit(i, dst->aspect_mask) { + unsigned aspect_mask = 1u << i; + VkFormat depth_format = 0; + if (aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT) + depth_format = vk_format_stencil_only(dst->image->vk_format); + else if (aspect_mask == VK_IMAGE_ASPECT_DEPTH_BIT) + depth_format = vk_format_depth_only(dst->image->vk_format); - itoi_bind_descriptors(cmd_buffer, &src_view, &dst_view); + create_iview(cmd_buffer, src, &src_view, depth_format, aspect_mask); + create_iview(cmd_buffer, dst, &dst_view, depth_format, aspect_mask); - VkPipeline pipeline = cmd_buffer->device->meta_state.itoi.pipeline[samples_log2]; - if (device->physical_device->rad_info.chip_class >= GFX9 && - (src->image->type == VK_IMAGE_TYPE_3D || dst->image->type == VK_IMAGE_TYPE_3D)) - pipeline = cmd_buffer->device->meta_state.itoi.pipeline_3d; - radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer), VK_PIPELINE_BIND_POINT_COMPUTE, - pipeline); + itoi_bind_descriptors(cmd_buffer, &src_view, &dst_view); - for (unsigned r = 0; r < num_rects; ++r) { - unsigned push_constants[6] = { - rects[r].src_x, rects[r].src_y, src->layer, rects[r].dst_x, rects[r].dst_y, dst->layer, - }; - radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer), - device->meta_state.itoi.img_p_layout, VK_SHADER_STAGE_COMPUTE_BIT, 0, - 24, push_constants); + VkPipeline pipeline = cmd_buffer->device->meta_state.itoi.pipeline[samples_log2]; + if (device->physical_device->rad_info.chip_class >= GFX9 && + (src->image->type == VK_IMAGE_TYPE_3D || dst->image->type == VK_IMAGE_TYPE_3D)) + pipeline = cmd_buffer->device->meta_state.itoi.pipeline_3d; + radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer), VK_PIPELINE_BIND_POINT_COMPUTE, + pipeline); - radv_unaligned_dispatch(cmd_buffer, rects[r].width, rects[r].height, 1); + for (unsigned r = 0; r < num_rects; ++r) { + unsigned push_constants[6] = { + rects[r].src_x, rects[r].src_y, src->layer, rects[r].dst_x, rects[r].dst_y, dst->layer, + }; + radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer), + device->meta_state.itoi.img_p_layout, VK_SHADER_STAGE_COMPUTE_BIT, 0, + 24, push_constants); + + radv_unaligned_dispatch(cmd_buffer, rects[r].width, rects[r].height, 1); + } } } @@ -1866,7 +1879,7 @@ radv_meta_clear_image_cs(struct radv_cmd_buffer *cmd_buffer, struct radv_meta_bl return; } - create_iview(cmd_buffer, dst, &dst_iview); + create_iview(cmd_buffer, dst, &dst_iview, VK_FORMAT_UNDEFINED, dst->aspect_mask); cleari_bind_descriptors(cmd_buffer, &dst_iview); VkPipeline pipeline = cmd_buffer->device->meta_state.cleari.pipeline[samples_log2];