From be48cf804b34b3318d642a6d4f46a59c37908759 Mon Sep 17 00:00:00 2001 From: Bas Nieuwenhuizen Date: Mon, 3 Aug 2020 01:05:07 +0200 Subject: [PATCH] amd/common: Store non-displayable DCC pitch. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit For DRM planes with modifiers. Reviewed-by: Marek Olšák Part-of: --- src/amd/common/ac_surface.c | 1 + src/amd/common/ac_surface.h | 1 + 2 files changed, 2 insertions(+) diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c index 223a61e4764..484db1d5550 100644 --- a/src/amd/common/ac_surface.c +++ b/src/amd/common/ac_surface.c @@ -1569,6 +1569,7 @@ static int gfx9_compute_miptree(struct ac_addrlib *addrlib, const struct radeon_ surf->u.gfx9.display_dcc_size = surf->dcc_size; surf->u.gfx9.display_dcc_alignment = surf->dcc_alignment; surf->u.gfx9.display_dcc_pitch_max = dout.pitch - 1; + surf->u.gfx9.dcc_pitch_max = dout.pitch - 1; /* Compute displayable DCC. */ if (in->flags.display && surf->num_dcc_levels && info->use_display_dcc_with_retile_blit) { diff --git a/src/amd/common/ac_surface.h b/src/amd/common/ac_surface.h index 5605ba7a3a6..ec6d044daf4 100644 --- a/src/amd/common/ac_surface.h +++ b/src/amd/common/ac_surface.h @@ -180,6 +180,7 @@ struct gfx9_surf_layout { uint32_t display_dcc_size; uint32_t display_dcc_alignment; uint16_t display_dcc_pitch_max; /* (mip chain pitch - 1) */ + uint16_t dcc_pitch_max; bool dcc_retile_use_uint16; /* if all values fit into uint16_t */ uint32_t dcc_retile_num_elements; void *dcc_retile_map;