From be28b566b0dd1972884e741250b54f127ca3460b Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Wed, 16 Mar 2022 17:52:35 +0100 Subject: [PATCH] radv: convert the meta clear path to dynamic rendering Signed-off-by: Samuel Pitoiset Reviewed-by: Jason Ekstrand Part-of: --- src/amd/vulkan/radv_meta_clear.c | 405 +++++++------------------------ src/amd/vulkan/radv_private.h | 2 - 2 files changed, 90 insertions(+), 317 deletions(-) diff --git a/src/amd/vulkan/radv_meta_clear.c b/src/amd/vulkan/radv_meta_clear.c index 525890ef84f..041ccb5c180 100644 --- a/src/amd/vulkan/radv_meta_clear.c +++ b/src/amd/vulkan/radv_meta_clear.c @@ -73,11 +73,13 @@ build_color_shaders(struct nir_shader **out_vs, struct nir_shader **out_fs, uint } static VkResult -create_pipeline(struct radv_device *device, struct radv_render_pass *render_pass, uint32_t samples, +create_pipeline(struct radv_device *device, uint32_t samples, struct nir_shader *vs_nir, struct nir_shader *fs_nir, const VkPipelineVertexInputStateCreateInfo *vi_state, const VkPipelineDepthStencilStateCreateInfo *ds_state, - const VkPipelineColorBlendStateCreateInfo *cb_state, const VkPipelineLayout layout, + const VkPipelineColorBlendStateCreateInfo *cb_state, + const VkPipelineRenderingCreateInfo *dyn_state, + const VkPipelineLayout layout, const struct radv_graphics_pipeline_create_info *extra, const VkAllocationCallbacks *alloc, VkPipeline *pipeline) { @@ -88,6 +90,7 @@ create_pipeline(struct radv_device *device, struct radv_render_pass *render_pass device_h, radv_pipeline_cache_to_handle(&device->meta_state.cache), &(VkGraphicsPipelineCreateInfo){ .sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO, + .pNext = dyn_state, .stageCount = fs_nir ? 2 : 1, .pStages = (VkPipelineShaderStageCreateInfo[]){ @@ -161,7 +164,7 @@ create_pipeline(struct radv_device *device, struct radv_render_pass *render_pass }, .layout = layout, .flags = 0, - .renderPass = radv_render_pass_to_handle(render_pass), + .renderPass = VK_NULL_HANDLE, .subpass = 0, }, extra, alloc, pipeline); @@ -172,85 +175,9 @@ create_pipeline(struct radv_device *device, struct radv_render_pass *render_pass return result; } -static VkResult -create_color_renderpass(struct radv_device *device, VkFormat vk_format, uint32_t samples, - unsigned attachment_index, VkRenderPass *pass) -{ - mtx_lock(&device->meta_state.mtx); - if (*pass) { - mtx_unlock(&device->meta_state.mtx); - return VK_SUCCESS; - } - - VkAttachmentReference2 color_refs[MAX_RTS]; - for (unsigned i = 0; i < MAX_RTS; ++i) { - color_refs[i] = (VkAttachmentReference2){ - .sType = VK_STRUCTURE_TYPE_ATTACHMENT_REFERENCE_2, - .attachment = i == attachment_index ? 0 : VK_ATTACHMENT_UNUSED, - .layout = VK_IMAGE_LAYOUT_GENERAL, - }; - } - - VkResult result = radv_CreateRenderPass2( - radv_device_to_handle(device), - &(VkRenderPassCreateInfo2){ - .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO_2, - .attachmentCount = 1, - .pAttachments = - &(VkAttachmentDescription2){ - .sType = VK_STRUCTURE_TYPE_ATTACHMENT_DESCRIPTION_2, - .format = vk_format, - .samples = samples, - .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD, - .storeOp = VK_ATTACHMENT_STORE_OP_STORE, - .initialLayout = VK_IMAGE_LAYOUT_GENERAL, - .finalLayout = VK_IMAGE_LAYOUT_GENERAL, - }, - .subpassCount = 1, - .pSubpasses = - &(VkSubpassDescription2){ - .sType = VK_STRUCTURE_TYPE_SUBPASS_DESCRIPTION_2, - .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS, - .inputAttachmentCount = 0, - .colorAttachmentCount = MAX_RTS, - .pColorAttachments = color_refs, - .pResolveAttachments = NULL, - .pDepthStencilAttachment = - &(VkAttachmentReference2){ - .sType = VK_STRUCTURE_TYPE_ATTACHMENT_REFERENCE_2, - .attachment = VK_ATTACHMENT_UNUSED, - .layout = VK_IMAGE_LAYOUT_GENERAL, - }, - .preserveAttachmentCount = 0, - .pPreserveAttachments = NULL, - }, - .dependencyCount = 2, - .pDependencies = - (VkSubpassDependency2[]){{.sType = VK_STRUCTURE_TYPE_SUBPASS_DEPENDENCY_2, - .srcSubpass = VK_SUBPASS_EXTERNAL, - .dstSubpass = 0, - .srcStageMask = VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT, - .dstStageMask = VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT, - .srcAccessMask = 0, - .dstAccessMask = 0, - .dependencyFlags = 0}, - {.sType = VK_STRUCTURE_TYPE_SUBPASS_DEPENDENCY_2, - .srcSubpass = 0, - .dstSubpass = VK_SUBPASS_EXTERNAL, - .srcStageMask = VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT, - .dstStageMask = VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT, - .srcAccessMask = 0, - .dstAccessMask = 0, - .dependencyFlags = 0}}, - }, - &device->meta_state.alloc, pass); - mtx_unlock(&device->meta_state.mtx); - return result; -} - static VkResult create_color_pipeline(struct radv_device *device, uint32_t samples, uint32_t frag_output, - VkPipeline *pipeline, VkRenderPass pass) + VkFormat format, VkPipeline *pipeline) { struct nir_shader *vs_nir; struct nir_shader *fs_nir; @@ -291,12 +218,21 @@ create_color_pipeline(struct radv_device *device, uint32_t samples, uint32_t fra .attachmentCount = MAX_RTS, .pAttachments = blend_attachment_state}; + VkFormat att_formats[MAX_RTS] = { 0 }; + att_formats[frag_output] = format; + + const VkPipelineRenderingCreateInfo rendering_create_info = { + .sType = VK_STRUCTURE_TYPE_PIPELINE_RENDERING_CREATE_INFO, + .colorAttachmentCount = MAX_RTS, + .pColorAttachmentFormats = att_formats, + }; + struct radv_graphics_pipeline_create_info extra = { .use_rectlist = true, }; result = - create_pipeline(device, radv_render_pass_from_handle(pass), samples, vs_nir, fs_nir, - &vi_state, &ds_state, &cb_state, device->meta_state.clear_color_p_layout, + create_pipeline(device, samples, vs_nir, fs_nir, &vi_state, &ds_state, &cb_state, + &rendering_create_info, device->meta_state.clear_color_p_layout, &extra, &device->meta_state.alloc, pipeline); mtx_unlock(&device->meta_state.mtx); @@ -341,8 +277,6 @@ radv_device_finish_meta_clear_state(struct radv_device *device) for (uint32_t k = 0; k < ARRAY_SIZE(state->color_clear[i][j].color_pipelines); ++k) { radv_DestroyPipeline(radv_device_to_handle(device), state->color_clear[i][j].color_pipelines[k], &state->alloc); - radv_DestroyRenderPass(radv_device_to_handle(device), - state->color_clear[i][j].render_pass[k], &state->alloc); } } } @@ -365,8 +299,6 @@ radv_device_finish_meta_clear_state(struct radv_device *device) state->ds_clear[i].depthstencil_unrestricted_pipeline[j], &state->alloc); } - radv_DestroyRenderPass(radv_device_to_handle(device), state->ds_clear[i].depthstencil_rp, - &state->alloc); } radv_DestroyPipelineLayout(radv_device_to_handle(device), state->clear_color_p_layout, &state->alloc); @@ -412,26 +344,12 @@ emit_color_clear(struct radv_cmd_buffer *cmd_buffer, const VkClearAttachment *cl fs_key = radv_format_meta_fs_key(device, format); assert(fs_key != -1); - if (device->meta_state.color_clear[samples_log2][clear_att->colorAttachment] - .render_pass[fs_key] == VK_NULL_HANDLE) { - VkResult ret = create_color_renderpass( - device, radv_fs_key_format_exemplars[fs_key], samples, clear_att->colorAttachment, - &device->meta_state.color_clear[samples_log2][clear_att->colorAttachment] - .render_pass[fs_key]); - if (ret != VK_SUCCESS) { - cmd_buffer->record_result = ret; - return; - } - } - if (device->meta_state.color_clear[samples_log2][clear_att->colorAttachment] .color_pipelines[fs_key] == VK_NULL_HANDLE) { VkResult ret = create_color_pipeline( - device, samples, clear_att->colorAttachment, + device, samples, clear_att->colorAttachment, radv_fs_key_format_exemplars[fs_key], &device->meta_state.color_clear[samples_log2][clear_att->colorAttachment] - .color_pipelines[fs_key], - device->meta_state.color_clear[samples_log2][clear_att->colorAttachment] - .render_pass[fs_key]); + .color_pipelines[fs_key]); if (ret != VK_SUCCESS) { cmd_buffer->record_result = ret; return; @@ -518,76 +436,9 @@ build_depthstencil_shader(struct nir_shader **out_vs, struct nir_shader **out_fs *out_fs = fs_b.shader; } -static VkResult -create_depthstencil_renderpass(struct radv_device *device, uint32_t samples, - VkRenderPass *render_pass) -{ - mtx_lock(&device->meta_state.mtx); - if (*render_pass) { - mtx_unlock(&device->meta_state.mtx); - return VK_SUCCESS; - } - - VkResult result = radv_CreateRenderPass2( - radv_device_to_handle(device), - &(VkRenderPassCreateInfo2){ - .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO_2, - .attachmentCount = 1, - .pAttachments = - &(VkAttachmentDescription2){ - .sType = VK_STRUCTURE_TYPE_ATTACHMENT_DESCRIPTION_2, - .format = VK_FORMAT_D32_SFLOAT_S8_UINT, - .samples = samples, - .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD, - .storeOp = VK_ATTACHMENT_STORE_OP_STORE, - .initialLayout = VK_IMAGE_LAYOUT_GENERAL, - .finalLayout = VK_IMAGE_LAYOUT_GENERAL, - }, - .subpassCount = 1, - .pSubpasses = - &(VkSubpassDescription2){ - .sType = VK_STRUCTURE_TYPE_SUBPASS_DESCRIPTION_2, - .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS, - .inputAttachmentCount = 0, - .colorAttachmentCount = 0, - .pColorAttachments = NULL, - .pResolveAttachments = NULL, - .pDepthStencilAttachment = - &(VkAttachmentReference2){ - .sType = VK_STRUCTURE_TYPE_ATTACHMENT_REFERENCE_2, - .attachment = 0, - .layout = VK_IMAGE_LAYOUT_GENERAL, - }, - .preserveAttachmentCount = 0, - .pPreserveAttachments = NULL, - }, - .dependencyCount = 2, - .pDependencies = - (VkSubpassDependency2[]){{.sType = VK_STRUCTURE_TYPE_SUBPASS_DEPENDENCY_2, - .srcSubpass = VK_SUBPASS_EXTERNAL, - .dstSubpass = 0, - .srcStageMask = VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT, - .dstStageMask = VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT, - .srcAccessMask = 0, - .dstAccessMask = 0, - .dependencyFlags = 0}, - {.sType = VK_STRUCTURE_TYPE_SUBPASS_DEPENDENCY_2, - .srcSubpass = 0, - .dstSubpass = VK_SUBPASS_EXTERNAL, - .srcStageMask = VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT, - .dstStageMask = VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT, - .srcAccessMask = 0, - .dstAccessMask = 0, - .dependencyFlags = 0}}}, - &device->meta_state.alloc, render_pass); - mtx_unlock(&device->meta_state.mtx); - return result; -} - static VkResult create_depthstencil_pipeline(struct radv_device *device, VkImageAspectFlags aspects, - uint32_t samples, int index, bool unrestricted, VkPipeline *pipeline, - VkRenderPass render_pass) + uint32_t samples, int index, bool unrestricted, VkPipeline *pipeline) { struct nir_shader *vs_nir, *fs_nir; VkResult result; @@ -630,6 +481,14 @@ create_depthstencil_pipeline(struct radv_device *device, VkImageAspectFlags aspe .pAttachments = NULL, }; + const VkPipelineRenderingCreateInfo rendering_create_info = { + .sType = VK_STRUCTURE_TYPE_PIPELINE_RENDERING_CREATE_INFO, + .depthAttachmentFormat = + (aspects & VK_IMAGE_ASPECT_DEPTH_BIT) ? VK_FORMAT_D32_SFLOAT : VK_FORMAT_UNDEFINED, + .stencilAttachmentFormat = + (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) ? VK_FORMAT_S8_UINT : VK_FORMAT_UNDEFINED, + }; + struct radv_graphics_pipeline_create_info extra = { .use_rectlist = true, }; @@ -641,9 +500,9 @@ create_depthstencil_pipeline(struct radv_device *device, VkImageAspectFlags aspe extra.db_stencil_clear = index == DEPTH_CLEAR_SLOW ? false : true; } result = - create_pipeline(device, radv_render_pass_from_handle(render_pass), samples, vs_nir, fs_nir, - &vi_state, &ds_state, &cb_state, device->meta_state.clear_depth_p_layout, - &extra, &device->meta_state.alloc, pipeline); + create_pipeline(device, samples, vs_nir, fs_nir, &vi_state, &ds_state, &cb_state, + &rendering_create_info, device->meta_state.clear_depth_p_layout, &extra, + &device->meta_state.alloc, pipeline); mtx_unlock(&device->meta_state.mtx); return result; @@ -709,20 +568,9 @@ pick_depthstencil_pipeline(struct radv_cmd_buffer *cmd_buffer, struct radv_meta_ unreachable("expected depth or stencil aspect"); } - if (cmd_buffer->device->meta_state.ds_clear[samples_log2].depthstencil_rp == VK_NULL_HANDLE) { - VkResult ret = create_depthstencil_renderpass( - cmd_buffer->device, 1u << samples_log2, - &cmd_buffer->device->meta_state.ds_clear[samples_log2].depthstencil_rp); - if (ret != VK_SUCCESS) { - cmd_buffer->record_result = ret; - return VK_NULL_HANDLE; - } - } - if (*pipeline == VK_NULL_HANDLE) { VkResult ret = create_depthstencil_pipeline( - cmd_buffer->device, aspects, 1u << samples_log2, index, unrestricted, pipeline, - cmd_buffer->device->meta_state.ds_clear[samples_log2].depthstencil_rp); + cmd_buffer->device, aspects, 1u << samples_log2, index, unrestricted, pipeline); if (ret != VK_SUCCESS) { cmd_buffer->record_result = ret; return VK_NULL_HANDLE; @@ -1344,14 +1192,8 @@ radv_device_init_meta_clear_state(struct radv_device *device, bool on_demand) unsigned fs_key = radv_format_meta_fs_key(device, format); assert(!state->color_clear[i][0].color_pipelines[fs_key]); - res = create_color_renderpass(device, format, samples, 0, - &state->color_clear[i][0].render_pass[fs_key]); - if (res != VK_SUCCESS) - goto fail; - - res = create_color_pipeline(device, samples, 0, - &state->color_clear[i][0].color_pipelines[fs_key], - state->color_clear[i][0].render_pass[fs_key]); + res = create_color_pipeline(device, samples, 0, format, + &state->color_clear[i][0].color_pipelines[fs_key]); if (res != VK_SUCCESS) goto fail; } @@ -1359,46 +1201,37 @@ radv_device_init_meta_clear_state(struct radv_device *device, bool on_demand) for (uint32_t i = 0; i < ARRAY_SIZE(state->ds_clear); ++i) { uint32_t samples = 1 << i; - res = create_depthstencil_renderpass(device, samples, &state->ds_clear[i].depthstencil_rp); - if (res != VK_SUCCESS) - goto fail; - for (uint32_t j = 0; j < NUM_DEPTH_CLEAR_PIPELINES; j++) { res = create_depthstencil_pipeline(device, VK_IMAGE_ASPECT_DEPTH_BIT, samples, j, false, - &state->ds_clear[i].depth_only_pipeline[j], - state->ds_clear[i].depthstencil_rp); + &state->ds_clear[i].depth_only_pipeline[j]); if (res != VK_SUCCESS) goto fail; res = create_depthstencil_pipeline(device, VK_IMAGE_ASPECT_STENCIL_BIT, samples, j, false, - &state->ds_clear[i].stencil_only_pipeline[j], - state->ds_clear[i].depthstencil_rp); + &state->ds_clear[i].stencil_only_pipeline[j]); if (res != VK_SUCCESS) goto fail; res = create_depthstencil_pipeline( device, VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT, samples, j, false, - &state->ds_clear[i].depthstencil_pipeline[j], state->ds_clear[i].depthstencil_rp); + &state->ds_clear[i].depthstencil_pipeline[j]); if (res != VK_SUCCESS) goto fail; res = create_depthstencil_pipeline(device, VK_IMAGE_ASPECT_DEPTH_BIT, samples, j, true, - &state->ds_clear[i].depth_only_unrestricted_pipeline[j], - state->ds_clear[i].depthstencil_rp); + &state->ds_clear[i].depth_only_unrestricted_pipeline[j]); if (res != VK_SUCCESS) goto fail; res = create_depthstencil_pipeline(device, VK_IMAGE_ASPECT_STENCIL_BIT, samples, j, true, - &state->ds_clear[i].stencil_only_unrestricted_pipeline[j], - state->ds_clear[i].depthstencil_rp); + &state->ds_clear[i].stencil_only_unrestricted_pipeline[j]); if (res != VK_SUCCESS) goto fail; res = create_depthstencil_pipeline( device, VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT, samples, j, true, - &state->ds_clear[i].depthstencil_unrestricted_pipeline[j], - state->ds_clear[i].depthstencil_rp); + &state->ds_clear[i].depthstencil_unrestricted_pipeline[j]); if (res != VK_SUCCESS) goto fail; } @@ -2122,7 +1955,6 @@ radv_clear_image_layer(struct radv_cmd_buffer *cmd_buffer, struct radv_image *im VkFormat format, int level, unsigned layer_count, const VkClearValue *clear_val) { - VkDevice device_h = radv_device_to_handle(cmd_buffer->device); struct radv_image_view iview; uint32_t width = radv_minify(image->info.width, range->baseMipLevel + level); uint32_t height = radv_minify(image->info.height, range->baseMipLevel + level); @@ -2141,109 +1973,6 @@ radv_clear_image_layer(struct radv_cmd_buffer *cmd_buffer, struct radv_image *im }, NULL); - VkFramebuffer fb; - radv_CreateFramebuffer( - device_h, - &(VkFramebufferCreateInfo){.sType = VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO, - .attachmentCount = 1, - .pAttachments = - (VkImageView[]){ - radv_image_view_to_handle(&iview), - }, - .width = width, - .height = height, - .layers = layer_count}, - &cmd_buffer->pool->vk.alloc, &fb); - - VkAttachmentDescription2 att_desc = { - .sType = VK_STRUCTURE_TYPE_ATTACHMENT_DESCRIPTION_2, - .format = iview.vk_format, - .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD, - .storeOp = VK_ATTACHMENT_STORE_OP_STORE, - .stencilLoadOp = VK_ATTACHMENT_LOAD_OP_LOAD, - .stencilStoreOp = VK_ATTACHMENT_STORE_OP_STORE, - .initialLayout = image_layout, - .finalLayout = image_layout, - }; - - VkSubpassDescription2 subpass_desc = { - .sType = VK_STRUCTURE_TYPE_SUBPASS_DESCRIPTION_2, - .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS, - .inputAttachmentCount = 0, - .colorAttachmentCount = 0, - .pColorAttachments = NULL, - .pResolveAttachments = NULL, - .pDepthStencilAttachment = NULL, - .preserveAttachmentCount = 0, - .pPreserveAttachments = NULL, - }; - - const VkAttachmentReference2 att_ref = { - .sType = VK_STRUCTURE_TYPE_ATTACHMENT_REFERENCE_2, - .attachment = 0, - .layout = image_layout, - }; - - if (range->aspectMask & VK_IMAGE_ASPECT_COLOR_BIT) { - subpass_desc.colorAttachmentCount = 1; - subpass_desc.pColorAttachments = &att_ref; - } else { - subpass_desc.pDepthStencilAttachment = &att_ref; - } - - VkRenderPass pass; - radv_CreateRenderPass2( - device_h, - &(VkRenderPassCreateInfo2){ - .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO_2, - .attachmentCount = 1, - .pAttachments = &att_desc, - .subpassCount = 1, - .pSubpasses = &subpass_desc, - .dependencyCount = 2, - .pDependencies = - (VkSubpassDependency2[]){{.sType = VK_STRUCTURE_TYPE_SUBPASS_DEPENDENCY_2, - .srcSubpass = VK_SUBPASS_EXTERNAL, - .dstSubpass = 0, - .srcStageMask = VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT, - .dstStageMask = VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT, - .srcAccessMask = 0, - .dstAccessMask = 0, - .dependencyFlags = 0}, - {.sType = VK_STRUCTURE_TYPE_SUBPASS_DEPENDENCY_2, - .srcSubpass = 0, - .dstSubpass = VK_SUBPASS_EXTERNAL, - .srcStageMask = VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT, - .dstStageMask = VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT, - .srcAccessMask = 0, - .dstAccessMask = 0, - .dependencyFlags = 0}}}, - &cmd_buffer->pool->vk.alloc, &pass); - - radv_cmd_buffer_begin_render_pass(cmd_buffer, - &(VkRenderPassBeginInfo){ - .sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO, - .renderArea = - { - .offset = - { - 0, - 0, - }, - .extent = - { - .width = width, - .height = height, - }, - }, - .renderPass = pass, - .framebuffer = fb, - .clearValueCount = 0, - .pClearValues = NULL, - }); - - radv_cmd_buffer_set_subpass(cmd_buffer, &cmd_buffer->state.pass->subpasses[0]); - VkClearAttachment clear_att = { .aspectMask = range->aspectMask, .colorAttachment = 0, @@ -2260,12 +1989,58 @@ radv_clear_image_layer(struct radv_cmd_buffer *cmd_buffer, struct radv_image *im .layerCount = layer_count, }; + VkRenderingAttachmentInfo color_att = {0}, depth_att = {0}, stencil_att = {0}; + + if (range->aspectMask & VK_IMAGE_ASPECT_COLOR_BIT) { + color_att.sType = VK_STRUCTURE_TYPE_RENDERING_ATTACHMENT_INFO; + color_att.imageView = radv_image_view_to_handle(&iview); + color_att.imageLayout = image_layout; + color_att.loadOp = VK_ATTACHMENT_LOAD_OP_LOAD; + color_att.storeOp = VK_ATTACHMENT_STORE_OP_STORE; + } else { + if (range->aspectMask & VK_IMAGE_ASPECT_DEPTH_BIT) { + depth_att.sType = VK_STRUCTURE_TYPE_RENDERING_ATTACHMENT_INFO; + depth_att.imageView = radv_image_view_to_handle(&iview); + depth_att.imageLayout = image_layout; + depth_att.loadOp = VK_ATTACHMENT_LOAD_OP_LOAD; + depth_att.storeOp = VK_ATTACHMENT_STORE_OP_STORE; + } + + if (range->aspectMask & VK_IMAGE_ASPECT_STENCIL_BIT) { + stencil_att.sType = VK_STRUCTURE_TYPE_RENDERING_ATTACHMENT_INFO; + stencil_att.imageView = radv_image_view_to_handle(&iview); + stencil_att.imageLayout = image_layout; + stencil_att.loadOp = VK_ATTACHMENT_LOAD_OP_LOAD; + stencil_att.storeOp = VK_ATTACHMENT_STORE_OP_STORE; + } + } + + VkRenderingInfo rendering_info = { + .sType = VK_STRUCTURE_TYPE_RENDERING_INFO, + .renderArea = { + .offset = { 0, 0 }, + .extent = { width, height }, + }, + .layerCount = layer_count, + }; + + if (range->aspectMask & VK_IMAGE_ASPECT_COLOR_BIT) { + rendering_info.colorAttachmentCount = 1; + rendering_info.pColorAttachments = &color_att; + } else { + if (range->aspectMask & VK_IMAGE_ASPECT_DEPTH_BIT) + rendering_info.pDepthAttachment = &depth_att; + if (range->aspectMask & VK_IMAGE_ASPECT_STENCIL_BIT) + rendering_info.pStencilAttachment = &stencil_att; + } + + radv_CmdBeginRendering(radv_cmd_buffer_to_handle(cmd_buffer), &rendering_info); + emit_clear(cmd_buffer, &clear_att, &clear_rect, NULL, NULL, 0, false); + radv_CmdEndRendering(radv_cmd_buffer_to_handle(cmd_buffer)); + radv_image_view_finish(&iview); - radv_cmd_buffer_end_render_pass(cmd_buffer); - radv_DestroyRenderPass(device_h, pass, &cmd_buffer->pool->vk.alloc); - radv_DestroyFramebuffer(device_h, fb, &cmd_buffer->pool->vk.alloc); } /** diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h index 196d1bf2154..d99243a3abe 100644 --- a/src/amd/vulkan/radv_private.h +++ b/src/amd/vulkan/radv_private.h @@ -454,12 +454,10 @@ struct radv_meta_state { * Use array element `i` for images with `2^i` samples. */ struct { - VkRenderPass render_pass[NUM_META_FS_KEYS]; VkPipeline color_pipelines[NUM_META_FS_KEYS]; } color_clear[MAX_SAMPLES_LOG2][MAX_RTS]; struct { - VkRenderPass depthstencil_rp; VkPipeline depth_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES]; VkPipeline stencil_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES]; VkPipeline depthstencil_pipeline[NUM_DEPTH_CLEAR_PIPELINES];