From be235ce93813e9e610f9dece9b1e4a3df96241d0 Mon Sep 17 00:00:00 2001
From: Kenneth Graunke <kenneth@whitecape.org>
Date: Mon, 5 Jun 2023 14:14:09 -0700
Subject: [PATCH] intel/genxml: Drop Tiled Resource Mode fields
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Neither RENDER_SURFACE_STATE nor VDENC_SURFACE_CONTROL_BITS have a
Tiled Resource Mode field anymore.  The RENDER_SURFACE_STATE field
was also overlapping with the L1 Cache Control settings field.

This also drops the assignment of that field in isl, because we were
just explicitly setting it to NONE (0) which is already the default
value genxml packing will give us.  That saves us some ifdefs.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23449>
---
 src/intel/genxml/gen125.xml       | 12 ------------
 src/intel/isl/isl_surface_state.c |  1 -
 2 files changed, 13 deletions(-)

diff --git a/src/intel/genxml/gen125.xml b/src/intel/genxml/gen125.xml
index 37cf19685d4..3ba0685c0be 100644
--- a/src/intel/genxml/gen125.xml
+++ b/src/intel/genxml/gen125.xml
@@ -803,13 +803,6 @@
       <value name="WT" value="3" />
       <value name="WS" value="4" />
     </field>
-    <field name="Tiled Resource Mode" start="178" end="179" type="uint">
-      <value name="NONE" value="0" />
-      <value name="4KB" value="1" />
-      <value name="64KB" value="2" />
-      <value name="TILEYF" value="1" />
-      <value name="TILEYS" value="2" />
-    </field>
     <field name="EWA Disable For Cube" start="180" end="180" type="bool" />
     <field name="Y Offset" start="181" end="183" type="uint" />
     <field name="X Offset" start="185" end="191" type="uint" />
@@ -1207,11 +1200,6 @@
     <field name="Memory Compression Enable" start="9" end="9" type="bool" />
     <field name="Memory Compression Mode" start="10" end="10" type="uint" />
     <field name="Cache Select" start="12" end="12" type="uint" />
-    <field name="Tiled Resource Mode" start="13" end="14" type="uint">
-      <value name="TRMODE_NONE" value="0" />
-      <value name="TRMODE_TILEYF" value="1" />
-      <value name="TRMODE_TILEYS" value="2" />
-    </field>
   </struct>
   <struct name="VDENC_PICTURE" length="3">
     <field name="Address" start="0" end="63" type="address" />
diff --git a/src/intel/isl/isl_surface_state.c b/src/intel/isl/isl_surface_state.c
index f7fd331ea8f..73cd71b515e 100644
--- a/src/intel/isl/isl_surface_state.c
+++ b/src/intel/isl/isl_surface_state.c
@@ -427,7 +427,6 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state,
    /* We don't use miptails yet.  The PRM recommends that you set "Mip Tail
     * Start LOD" to 15 to prevent the hardware from trying to use them.
     */
-   s.TiledResourceMode = NONE;
    s.MipTailStartLOD = 15;
 #endif