diff --git a/src/gallium/drivers/panfrost/pan_screen.c b/src/gallium/drivers/panfrost/pan_screen.c index 0db0837bb2f..0d2620fcc7c 100644 --- a/src/gallium/drivers/panfrost/pan_screen.c +++ b/src/gallium/drivers/panfrost/pan_screen.c @@ -121,120 +121,6 @@ from_kmod_group_allow_priority_flags( return flags; } -static int -panfrost_get_shader_param(struct pipe_screen *screen, - enum pipe_shader_type shader, - enum pipe_shader_cap param) -{ - struct panfrost_device *dev = pan_device(screen); - bool is_nofp16 = dev->debug & PAN_DBG_NOFP16; - - switch (shader) { - case PIPE_SHADER_VERTEX: - case PIPE_SHADER_FRAGMENT: - case PIPE_SHADER_COMPUTE: - break; - default: - return 0; - } - - /* We only allow observable side effects (memory writes) in compute and - * fragment shaders. Side effects in the geometry pipeline cause - * trouble with IDVS and conflict with our transform feedback lowering. - */ - bool allow_side_effects = (shader != PIPE_SHADER_VERTEX); - - switch (param) { - case PIPE_SHADER_CAP_MAX_INSTRUCTIONS: - case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS: - case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS: - case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS: - return 16384; /* arbitrary */ - - case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH: - return 1024; /* arbitrary */ - - case PIPE_SHADER_CAP_MAX_INPUTS: - /* Used as ABI on Midgard */ - return 16; - - case PIPE_SHADER_CAP_MAX_OUTPUTS: - return shader == PIPE_SHADER_FRAGMENT ? 8 : PIPE_MAX_ATTRIBS; - - case PIPE_SHADER_CAP_MAX_TEMPS: - return 256; /* arbitrary */ - - case PIPE_SHADER_CAP_MAX_CONST_BUFFER0_SIZE: - return 16 * 1024 * sizeof(float); - - case PIPE_SHADER_CAP_MAX_CONST_BUFFERS: - STATIC_ASSERT(PAN_MAX_CONST_BUFFERS < 0x100); - return PAN_MAX_CONST_BUFFERS; - - case PIPE_SHADER_CAP_CONT_SUPPORTED: - return 0; - - case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR: - return dev->arch >= 6; - - case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR: - return 1; - - case PIPE_SHADER_CAP_SUBROUTINES: - return 0; - - case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED: - return 0; - - case PIPE_SHADER_CAP_INTEGERS: - return 1; - - /* The Bifrost compiler supports full 16-bit. Midgard could but int16 - * support is untested, so restrict INT16 to Bifrost. Midgard - * architecturally cannot support fp16 derivatives. */ - - case PIPE_SHADER_CAP_FP16: - case PIPE_SHADER_CAP_GLSL_16BIT_CONSTS: - return !is_nofp16; - case PIPE_SHADER_CAP_FP16_DERIVATIVES: - case PIPE_SHADER_CAP_FP16_CONST_BUFFERS: - return dev->arch >= 6 && !is_nofp16; - case PIPE_SHADER_CAP_INT16: - /* Blocked on https://gitlab.freedesktop.org/mesa/mesa/-/issues/6075 */ - return false; - - case PIPE_SHADER_CAP_INT64_ATOMICS: - case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE: - return 0; - - case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS: - STATIC_ASSERT(PIPE_MAX_SAMPLERS < 0x10000); - return PIPE_MAX_SAMPLERS; - - case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS: - STATIC_ASSERT(PIPE_MAX_SHADER_SAMPLER_VIEWS < 0x10000); - return PIPE_MAX_SHADER_SAMPLER_VIEWS; - - case PIPE_SHADER_CAP_SUPPORTED_IRS: - return (1 << PIPE_SHADER_IR_NIR); - - case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS: - return allow_side_effects ? 16 : 0; - - case PIPE_SHADER_CAP_MAX_SHADER_IMAGES: - return allow_side_effects ? PIPE_MAX_SHADER_IMAGES : 0; - - case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS: - case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS: - return 0; - - default: - return 0; - } - - return 0; -} - static uint32_t pipe_to_pan_bind_flags(uint32_t pipe_bind_flags) { @@ -446,116 +332,6 @@ panfrost_is_dmabuf_modifier_supported(struct pipe_screen *screen, return count > 0; } -static int -panfrost_get_compute_param(struct pipe_screen *pscreen, - enum pipe_compute_cap param, void *ret) -{ - struct panfrost_device *dev = pan_device(pscreen); - const char *const ir = "panfrost"; - -#define RET(x) \ - do { \ - if (ret) \ - memcpy(ret, x, sizeof(x)); \ - return sizeof(x); \ - } while (0) - - switch (param) { - case PIPE_COMPUTE_CAP_ADDRESS_BITS: - RET((uint32_t[]){64}); - - case PIPE_COMPUTE_CAP_IR_TARGET: - if (ret) - sprintf(ret, "%s", ir); - return strlen(ir) * sizeof(char); - - case PIPE_COMPUTE_CAP_GRID_DIMENSION: - RET((uint64_t[]){3}); - - case PIPE_COMPUTE_CAP_MAX_GRID_SIZE: - RET(((uint64_t[]){65535, 65535, 65535})); - - case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE: - /* Unpredictable behaviour at larger sizes. Mali-G52 advertises - * 384x384x384. - * - * On Midgard, we don't allow more than 128 threads in each - * direction to match PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK. - * That still exceeds the minimum-maximum. - */ - if (dev->arch >= 6) - RET(((uint64_t[]){256, 256, 256})); - else - RET(((uint64_t[]){128, 128, 128})); - - case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK: - /* On Bifrost and newer, all GPUs can support at least 256 threads - * regardless of register usage, so we report 256. - * - * On Midgard, with maximum register usage, the maximum - * thread count is only 64. We would like to report 64 here, but - * the GLES3.1 spec minimum is 128, so we report 128 and limit - * the register allocation of affected compute kernels. - */ - RET((uint64_t[]){dev->arch >= 6 ? 256 : 128}); - - case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: - case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE: { - uint64_t total_ram; - - if (!os_get_total_physical_memory(&total_ram)) - return 0; - - /* We don't want to burn too much ram with the GPU. If the user has 4GiB - * or less, we use at most half. If they have more than 4GiB, we use 3/4. - */ - uint64_t available_ram; - if (total_ram <= 4ull * 1024 * 1024 * 1024) - available_ram = total_ram / 2; - else - available_ram = total_ram * 3 / 4; - - /* 48bit address space max, with the lower 32MB reserved. We clamp - * things so it matches kmod VA range limitations. - */ - uint64_t user_va_start = - panfrost_clamp_to_usable_va_range(dev->kmod.dev, PAN_VA_USER_START); - uint64_t user_va_end = - panfrost_clamp_to_usable_va_range(dev->kmod.dev, PAN_VA_USER_END); - - /* We cannot support more than the VA limit */ - RET((uint64_t[]){MIN2(available_ram, user_va_end - user_va_start)}); - } - - case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: - RET((uint64_t[]){32768}); - - case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: - case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: - RET((uint64_t[]){4096}); - - case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY: - RET((uint32_t[]){800 /* MHz -- TODO */}); - - case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS: - RET((uint32_t[]){dev->core_count}); - - case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED: - RET((uint32_t[]){1}); - - case PIPE_COMPUTE_CAP_SUBGROUP_SIZES: - RET((uint32_t[]){pan_subgroup_size(dev->arch)}); - - case PIPE_COMPUTE_CAP_MAX_SUBGROUPS: - RET((uint32_t[]){0 /* TODO */}); - - case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK: - RET((uint64_t[]){1024}); // TODO - } - - return 0; -} - static void panfrost_init_shader_caps(struct panfrost_screen *screen) { @@ -1072,8 +848,6 @@ panfrost_create_screen(int fd, const struct pipe_screen_config *config, screen->base.get_vendor = panfrost_get_vendor; screen->base.get_device_vendor = panfrost_get_device_vendor; screen->base.get_driver_query_info = panfrost_get_driver_query_info; - screen->base.get_shader_param = panfrost_get_shader_param; - screen->base.get_compute_param = panfrost_get_compute_param; screen->base.get_timestamp = panfrost_get_timestamp; screen->base.is_format_supported = panfrost_is_format_supported; screen->base.query_dmabuf_modifiers = panfrost_query_dmabuf_modifiers;