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r600c: add tiling support for evergreen+

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Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
This commit is contained in:
Alex Deucher 2011-06-14 18:47:11 -04:00
parent 338e8e5f14
commit bdc518e341
1 changed files with 95 additions and 45 deletions
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140
src/mesa/drivers/dri/radeon/radeon_screen.c
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@ -1640,52 +1640,102 @@ radeonCreateScreen2(__DRIscreen *sPriv)
screen->group_bytes = 512;
else
screen->group_bytes = 256;
if (IS_R600_CLASS(screen) && (sPriv->drm_version.minor >= 6) &&
(screen->chip_family < CHIP_FAMILY_CEDAR)) {
ret = radeonGetParam(sPriv, RADEON_INFO_TILE_CONFIG, &temp);
if (ret)
fprintf(stderr, "failed to get tiling info\n");
else {
screen->tile_config = temp;
screen->r7xx_bank_op = 0;
switch((screen->tile_config & 0xe) >> 1) {
case 0:
screen->num_channels = 1;
break;
case 1:
screen->num_channels = 2;
break;
case 2:
screen->num_channels = 4;
break;
case 3:
screen->num_channels = 8;
break;
default:
fprintf(stderr, "bad channels\n");
break;
if (IS_R600_CLASS(screen)) {
if ((sPriv->drm_version.minor >= 6) &&
(screen->chip_family < CHIP_FAMILY_CEDAR)) {
ret = radeonGetParam(sPriv, RADEON_INFO_TILE_CONFIG, &temp);
if (ret)
fprintf(stderr, "failed to get tiling info\n");
else {
screen->tile_config = temp;
screen->r7xx_bank_op = 0;
switch ((screen->tile_config & 0xe) >> 1) {
case 0:
screen->num_channels = 1;
break;
case 1:
screen->num_channels = 2;
break;
case 2:
screen->num_channels = 4;
break;
case 3:
screen->num_channels = 8;
break;
default:
fprintf(stderr, "bad channels\n");
break;
}
switch ((screen->tile_config & 0x30) >> 4) {
case 0:
screen->num_banks = 4;
break;
case 1:
screen->num_banks = 8;
break;
default:
fprintf(stderr, "bad banks\n");
break;
}
switch ((screen->tile_config & 0xc0) >> 6) {
case 0:
screen->group_bytes = 256;
break;
case 1:
screen->group_bytes = 512;
break;
default:
fprintf(stderr, "bad group_bytes\n");
break;
}
}
switch((screen->tile_config & 0x30) >> 4) {
case 0:
screen->num_banks = 4;
break;
case 1:
screen->num_banks = 8;
break;
default:
fprintf(stderr, "bad banks\n");
break;
}
switch((screen->tile_config & 0xc0) >> 6) {
case 0:
screen->group_bytes = 256;
break;
case 1:
screen->group_bytes = 512;
break;
default:
fprintf(stderr, "bad group_bytes\n");
break;
} else if ((sPriv->drm_version.minor >= 7) &&
(screen->chip_family >= CHIP_FAMILY_CEDAR)) {
ret = radeonGetParam(sPriv, RADEON_INFO_TILE_CONFIG, &temp);
if (ret)
fprintf(stderr, "failed to get tiling info\n");
else {
screen->tile_config = temp;
screen->r7xx_bank_op = 0;
switch (screen->tile_config & 0xf) {
case 0:
screen->num_channels = 1;
break;
case 1:
screen->num_channels = 2;
break;
case 2:
screen->num_channels = 4;
break;
case 3:
screen->num_channels = 8;
break;
default:
fprintf(stderr, "bad channels\n");
break;
}
switch ((screen->tile_config & 0xf0) >> 4) {
case 0:
screen->num_banks = 4;
break;
case 1:
screen->num_banks = 8;
break;
default:
fprintf(stderr, "bad banks\n");
break;
}
switch ((screen->tile_config & 0xf00) >> 8) {
case 0:
screen->group_bytes = 256;
break;
case 1:
screen->group_bytes = 512;
break;
default:
fprintf(stderr, "bad group_bytes\n");
break;
}
}
}
}