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i965/blorp: switch eu-emitter to use FS IR and fs_generator

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No regressions on IVB (piglit quick + unit tests).

v2 (Paul):
  - no need to patch the unit tests anymore. Original logic
    was altered and unit tests updated to match the
    fs-generator
  - lrp emission moves from the blorp compiler core into the
    emitter here (previously there was a separate refactoring
    patch which is not really needed anymore as the lrp logic
    got refactored when the original lrp logic got fixed).
  - pass 'BRW_BLORP_RENDERBUFFER_BINDING_TABLE_INDEX' to the
    generator in fs_inst::target instead of hardcoding it

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
This commit is contained in:
Topi Pohjolainen 2013-12-10 15:12:30 +02:00
parent 8f3e5363ad
commit bda88f121b
3 changed files with 83 additions and 119 deletions
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20
src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
View file

@ -654,11 +654,6 @@ private:
const sampler_message_arg *args, int num_args);
void render_target_write();
void emit_lrp(const struct brw_reg &dst,
const struct brw_reg &src1,
const struct brw_reg &src2,
const struct brw_reg &src3);
/**
* Base-2 logarithm of the maximum number of samples that can be blended.
*/
@ -1584,21 +1579,6 @@ brw_blorp_blit_program::manual_blend_average(unsigned num_samples)
emit_endif();
}
void
brw_blorp_blit_program::emit_lrp(const struct brw_reg &dst,
const struct brw_reg &src1,
const struct brw_reg &src2,
const struct brw_reg &src3)
{
brw_set_access_mode(&func, BRW_ALIGN_16);
brw_set_compression_control(&func, BRW_COMPRESSION_NONE);
brw_LRP(&func, dst, src1, src2, src3);
brw_set_compression_control(&func, BRW_COMPRESSION_2NDHALF);
brw_LRP(&func, sechalf(dst), sechalf(src1), sechalf(src2), sechalf(src3));
brw_set_compression_control(&func, BRW_COMPRESSION_COMPRESSED);
brw_set_access_mode(&func, BRW_ALIGN_1);
}
void
brw_blorp_blit_program::manual_blend_bilinear(unsigned num_samples)
{

118
src/mesa/drivers/dri/i965/brw_blorp_blit_eu.cpp
View file

@ -26,24 +26,9 @@
#include "brw_blorp.h"
brw_blorp_eu_emitter::brw_blorp_eu_emitter(struct brw_context *brw)
: mem_ctx(ralloc_context(NULL))
: mem_ctx(ralloc_context(NULL)), c(rzalloc(mem_ctx, struct brw_wm_compile)),
generator(brw, c, NULL, NULL, false)
{
brw_init_compile(brw, &func, mem_ctx);
/*
* By default everything is emitted as 16-wide with only a few expections
* handled explicitly either here in the compiler or by one of the specific
* code emission calls.
* It should be also noted that here in this file any alterations of the
* compression control settings are only used to affect the execution size
* of the instructions. The instruction template used to initialise all the
* instructions is effectively not altered -- the value stays at zero
* representing either GEN6_COMPRESSION_1Q or GEN6_COMPRESSION_1H depending
* on the context.
* If any other settings are used in the instruction headers, they are set
* elsewhere by the individual code emission calls.
*/
brw_set_compression_control(&func, BRW_COMPRESSION_COMPRESSED);
}
brw_blorp_eu_emitter::~brw_blorp_eu_emitter()
@ -54,15 +39,17 @@ brw_blorp_eu_emitter::~brw_blorp_eu_emitter()
const unsigned *
brw_blorp_eu_emitter::get_program(unsigned *program_size, FILE *dump_file)
{
brw_set_uip_jip(&func);
const unsigned *res;
if (unlikely(INTEL_DEBUG & DEBUG_BLORP)) {
printf("Native code for BLORP blit:\n");
brw_dump_compile(&func, dump_file, 0, func.next_insn_offset);
res = generator.generate_assembly(NULL, &insts, program_size, dump_file);
printf("\n");
} else {
res = generator.generate_assembly(NULL, &insts, program_size);
}
return brw_get_program(&func, program_size);
return res;
}
/**
@ -80,17 +67,15 @@ brw_blorp_eu_emitter::emit_kill_if_outside_rect(const struct brw_reg &x,
{
struct brw_reg f0 = brw_flag_reg(0, 0);
struct brw_reg g1 = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
struct brw_reg null32 = vec16(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD));
brw_CMP(&func, null32, BRW_CONDITIONAL_GE, x, dst_x0);
brw_CMP(&func, null32, BRW_CONDITIONAL_GE, y, dst_y0);
brw_CMP(&func, null32, BRW_CONDITIONAL_L, x, dst_x1);
brw_CMP(&func, null32, BRW_CONDITIONAL_L, y, dst_y1);
emit_cmp(BRW_CONDITIONAL_GE, x, dst_x0);
emit_cmp(BRW_CONDITIONAL_GE, y, dst_y0)->predicate = BRW_PREDICATE_NORMAL;
emit_cmp(BRW_CONDITIONAL_L, x, dst_x1)->predicate = BRW_PREDICATE_NORMAL;
emit_cmp(BRW_CONDITIONAL_L, y, dst_y1)->predicate = BRW_PREDICATE_NORMAL;
brw_set_predicate_control(&func, BRW_PREDICATE_NONE);
struct brw_instruction *inst = brw_AND(&func, g1, f0, g1);
inst->header.mask_control = BRW_MASK_DISABLE;
fs_inst *inst = new (mem_ctx) fs_inst(BRW_OPCODE_AND, g1, f0, g1);
inst->force_writemask_all = true;
insts.push_tail(inst);
}
void
@ -99,40 +84,14 @@ brw_blorp_eu_emitter::emit_texture_lookup(const struct brw_reg &dst,
unsigned base_mrf,
unsigned msg_length)
{
unsigned msg_type;
fs_inst *inst = new (mem_ctx) fs_inst(op, dst, brw_message_reg(base_mrf));
switch (op) {
case SHADER_OPCODE_TEX:
msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE;
break;
case SHADER_OPCODE_TXF:
msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
break;
case SHADER_OPCODE_TXF_CMS:
msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS;
break;
case SHADER_OPCODE_TXF_UMS:
msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS;
break;
case SHADER_OPCODE_TXF_MCS:
msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS;
break;
default:
assert(!"Unsupported texture lookup operation");
}
inst->base_mrf = base_mrf;
inst->mlen = msg_length;
inst->sampler = 0;
inst->header_present = false;
brw_SAMPLE(&func,
retype(dst, BRW_REGISTER_TYPE_UW) /* dest */,
base_mrf /* msg_reg_nr */,
brw_message_reg(base_mrf) /* src0 */,
BRW_BLORP_TEXTURE_BINDING_TABLE_INDEX,
0 /* sampler */,
msg_type,
8 /* response_length. TODO: should be smaller for non-RGBA formats? */,
msg_length,
0 /* header_present */,
BRW_SAMPLER_SIMD_MODE_SIMD16,
BRW_SAMPLER_RETURN_FORMAT_FLOAT32);
insts.push_tail(inst);
}
void
@ -141,16 +100,15 @@ brw_blorp_eu_emitter::emit_render_target_write(const struct brw_reg &src0,
unsigned msg_length,
bool use_header)
{
brw_fb_WRITE(&func,
16 /* dispatch_width */,
msg_reg_nr,
src0,
BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE,
BRW_BLORP_RENDERBUFFER_BINDING_TABLE_INDEX,
msg_length,
0 /* response_length */,
true /* eot */,
use_header);
fs_inst *inst = new (mem_ctx) fs_inst(FS_OPCODE_BLORP_FB_WRITE);
inst->src[0] = src0;
inst->base_mrf = msg_reg_nr;
inst->mlen = msg_length;
inst->header_present = use_header;
inst->target = BRW_BLORP_RENDERBUFFER_BINDING_TABLE_INDEX;
insts.push_tail(inst);
}
void
@ -161,8 +119,18 @@ brw_blorp_eu_emitter::emit_combine(enum opcode combine_opcode,
{
assert(combine_opcode == BRW_OPCODE_ADD || combine_opcode == BRW_OPCODE_AVG);
if (combine_opcode == BRW_OPCODE_ADD)
brw_ADD(&func, dst, src_1, src_2);
else
brw_AVG(&func, dst, src_1, src_2);
insts.push_tail(new (mem_ctx) fs_inst(combine_opcode, dst, src_1, src_2));
}
fs_inst *
brw_blorp_eu_emitter::emit_cmp(int op,
const struct brw_reg &x,
const struct brw_reg &y)
{
fs_inst *cmp = new (mem_ctx) fs_inst(BRW_OPCODE_CMP,
vec16(brw_null_reg()), x, y);
cmp->conditional_mod = op;
insts.push_tail(cmp);
return cmp;
}

64
src/mesa/drivers/dri/i965/brw_blorp_blit_eu.h
View file

@ -25,7 +25,7 @@
#define BRW_BLORP_BLIT_EU_H
#include "brw_context.h"
#include "brw_eu.h"
#include "brw_fs.h"
class brw_blorp_eu_emitter
{
@ -63,9 +63,11 @@ protected:
const struct brw_reg &dst,
const struct brw_reg &src)
{
brw_CMP(&func, vec16(brw_null_reg()), op, x, y);
brw_MOV(&func, dst, src);
brw_set_predicate_control(&func, BRW_PREDICATE_NONE);
emit_cmp(op, x, y);
fs_inst *mv = new (mem_ctx) fs_inst(BRW_OPCODE_MOV, dst, src);
mv->predicate = BRW_PREDICATE_NORMAL;
insts.push_tail(mv);
}
inline void emit_if_eq_mov(const struct brw_reg &x, unsigned y,
@ -74,101 +76,115 @@ protected:
emit_cond_mov(x, brw_imm_d(y), BRW_CONDITIONAL_EQ, dst, brw_imm_d(src));
}
inline void emit_lrp(const struct brw_reg &dst,
const struct brw_reg &src1,
const struct brw_reg &src2,
const struct brw_reg &src3)
{
insts.push_tail(
new (mem_ctx) fs_inst(BRW_OPCODE_LRP, dst, src1, src2, src3));
}
inline void emit_mov(const struct brw_reg& dst, const struct brw_reg& src)
{
brw_MOV(&func, dst, src);
insts.push_tail(new (mem_ctx) fs_inst(BRW_OPCODE_MOV, dst, src));
}
inline void emit_mov_8(const struct brw_reg& dst, const struct brw_reg& src)
{
brw_set_compression_control(&func, BRW_COMPRESSION_NONE);
emit_mov(dst, src);
brw_set_compression_control(&func, BRW_COMPRESSION_COMPRESSED);
fs_inst *mv = new (mem_ctx) fs_inst(BRW_OPCODE_MOV, dst, src);
mv->force_uncompressed = true;
insts.push_tail(mv);
}
inline void emit_and(const struct brw_reg& dst,
const struct brw_reg& src1,
const struct brw_reg& src2)
{
brw_AND(&func, dst, src1, src2);
insts.push_tail(new (mem_ctx) fs_inst(BRW_OPCODE_AND, dst, src1, src2));
}
inline void emit_add(const struct brw_reg& dst,
const struct brw_reg& src1,
const struct brw_reg& src2)
{
brw_ADD(&func, dst, src1, src2);
insts.push_tail(new (mem_ctx) fs_inst(BRW_OPCODE_ADD, dst, src1, src2));
}
inline void emit_add_8(const struct brw_reg& dst,
const struct brw_reg& src1,
const struct brw_reg& src2)
{
brw_set_compression_control(&func, BRW_COMPRESSION_NONE);
emit_add(dst, src1, src2);
brw_set_compression_control(&func, BRW_COMPRESSION_COMPRESSED);
fs_inst *add = new (mem_ctx) fs_inst(BRW_OPCODE_ADD, dst, src1, src2);
add->force_uncompressed = true;
insts.push_tail(add);
}
inline void emit_mul(const struct brw_reg& dst,
const struct brw_reg& src1,
const struct brw_reg& src2)
{
brw_MUL(&func, dst, src1, src2);
insts.push_tail(new (mem_ctx) fs_inst(BRW_OPCODE_MUL, dst, src1, src2));
}
inline void emit_shr(const struct brw_reg& dst,
const struct brw_reg& src1,
const struct brw_reg& src2)
{
brw_SHR(&func, dst, src1, src2);
insts.push_tail(new (mem_ctx) fs_inst(BRW_OPCODE_SHR, dst, src1, src2));
}
inline void emit_shl(const struct brw_reg& dst,
const struct brw_reg& src1,
const struct brw_reg& src2)
{
brw_SHL(&func, dst, src1, src2);
insts.push_tail(new (mem_ctx) fs_inst(BRW_OPCODE_SHL, dst, src1, src2));
}
inline void emit_or(const struct brw_reg& dst,
const struct brw_reg& src1,
const struct brw_reg& src2)
{
brw_OR(&func, dst, src1, src2);
insts.push_tail(new (mem_ctx) fs_inst(BRW_OPCODE_OR, dst, src1, src2));
}
inline void emit_frc(const struct brw_reg& dst,
const struct brw_reg& src)
{
brw_FRC(&func, dst, src);
insts.push_tail(new (mem_ctx) fs_inst(BRW_OPCODE_FRC, dst, src));
}
inline void emit_rndd(const struct brw_reg& dst,
const struct brw_reg& src)
{
brw_RNDD(&func, dst, src);
insts.push_tail(new (mem_ctx) fs_inst(BRW_OPCODE_RNDD, dst, src));
}
inline void emit_cmp_if(int op,
const struct brw_reg &x,
const struct brw_reg &y)
{
brw_CMP(&func, vec16(brw_null_reg()), op, x, y);
brw_IF(&func, BRW_EXECUTE_16);
emit_cmp(op, x, y);
insts.push_tail(new (mem_ctx) fs_inst(BRW_OPCODE_IF));
}
inline void emit_else(void)
{
brw_ELSE(&func);
insts.push_tail(new (mem_ctx) fs_inst(BRW_OPCODE_ELSE));
}
inline void emit_endif(void)
{
brw_ENDIF(&func);
insts.push_tail(new (mem_ctx) fs_inst(BRW_OPCODE_ENDIF));
}
private:
fs_inst *emit_cmp(int op, const struct brw_reg &x, const struct brw_reg &y);
void *mem_ctx;
struct brw_compile func;
struct brw_wm_compile *c;
exec_list insts;
fs_generator generator;
};
#endif /* BRW_BLORP_BLIT_EU_H */