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tu, ir3: Determine dual-src blend from shader for FS outputs
The other state in this register comes from the FS, so determine whether dual-source blending is enabled from the FS too, in order to avoid entangling FS state and output state that with graphics pipeline library can be in different pipelines. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18554>
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6c7da1b632
commit
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3 changed files with 11 additions and 12 deletions
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@ -4143,6 +4143,8 @@ setup_output(struct ir3_context *ctx, nir_intrinsic_instr *intr)
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so->color0_mrt = 1;
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} else {
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slot = FRAG_RESULT_DATA0 + io.dual_source_blend_index;
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if (io.dual_source_blend_index > 0)
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so->dual_src_blend = true;
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}
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break;
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case FRAG_RESULT_SAMPLE_MASK:
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@ -4153,6 +4155,8 @@ setup_output(struct ir3_context *ctx, nir_intrinsic_instr *intr)
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break;
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default:
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slot += io.dual_source_blend_index; /* For dual-src blend */
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if (io.dual_source_blend_index > 0)
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so->dual_src_blend = true;
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if (slot >= FRAG_RESULT_DATA0)
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break;
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ir3_context_error(ctx, "unknown FS output name: %s\n",
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@ -571,6 +571,9 @@ struct ir3_shader_variant {
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/* Whether multi-position output is enabled. */
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bool multi_pos_output;
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/* Whether dual-source blending is enabled. */
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bool dual_src_blend;
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/* Size in bytes of required shared memory */
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unsigned shared_size;
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@ -260,7 +260,6 @@ struct tu_pipeline_builder
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/* these states are affectd by rasterizer_discard */
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bool depth_clip_disable;
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bool use_color_attachments;
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bool use_dual_src_blend;
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bool alpha_to_coverage;
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uint32_t color_attachment_count;
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VkFormat color_attachment_formats[MAX_RTS];
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@ -1612,7 +1611,7 @@ tu6_emit_fs_inputs(struct tu_cs *cs, const struct ir3_shader_variant *fs)
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static void
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tu6_emit_fs_outputs(struct tu_cs *cs,
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const struct ir3_shader_variant *fs,
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uint32_t mrt_count, bool dual_src_blend,
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uint32_t mrt_count,
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bool no_earlyz,
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struct tu_pipeline *pipeline)
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{
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@ -1636,7 +1635,7 @@ tu6_emit_fs_outputs(struct tu_cs *cs,
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tu_cs_emit(cs, A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(posz_regid) |
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A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID(smask_regid) |
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A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID(stencilref_regid) |
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COND(dual_src_blend, A6XX_SP_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE));
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COND(fs->dual_src_blend, A6XX_SP_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE));
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tu_cs_emit(cs, A6XX_SP_FS_OUTPUT_CNTL1_MRT(mrt_count));
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/* There is no point in having component enabled which is not written
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@ -1663,7 +1662,7 @@ tu6_emit_fs_outputs(struct tu_cs *cs,
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tu_cs_emit(cs, COND(fs->writes_pos, A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_Z) |
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COND(fs->writes_smask, A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_SAMPMASK) |
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COND(fs->writes_stencilref, A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_STENCILREF) |
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COND(dual_src_blend, A6XX_RB_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE));
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COND(fs->dual_src_blend, A6XX_RB_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE));
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tu_cs_emit(cs, A6XX_RB_FS_OUTPUT_CNTL1_MRT(mrt_count));
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tu_cs_emit_regs(cs,
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@ -1876,7 +1875,6 @@ tu6_emit_program(struct tu_cs *cs,
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if (fs) {
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tu6_emit_fs_inputs(cs, fs);
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tu6_emit_fs_outputs(cs, fs, mrt_count,
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builder->use_dual_src_blend,
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no_earlyz,
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pipeline);
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} else {
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@ -1884,7 +1882,6 @@ tu6_emit_program(struct tu_cs *cs,
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struct ir3_shader_variant dummy_variant = {};
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tu6_emit_fs_inputs(cs, &dummy_variant);
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tu6_emit_fs_outputs(cs, &dummy_variant, mrt_count,
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builder->use_dual_src_blend,
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no_earlyz,
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NULL);
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}
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@ -3713,7 +3710,7 @@ tu_pipeline_builder_parse_multisample_and_color_blend(
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pipeline->blend.color_write_enable :
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pipeline->blend.blend_enable;
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tu6_emit_blend_control(pipeline, blend_enable_mask,
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builder->use_dual_src_blend, msaa_info);
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tu_blend_state_is_dual_src(blend_info), msaa_info);
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if (tu_pipeline_static_state(pipeline, &cs, TU_DYNAMIC_STATE_BLEND,
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blend_info->attachmentCount * 3 + 4)) {
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@ -4066,11 +4063,6 @@ tu_pipeline_builder_init_graphics(
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if (!builder->rasterizer_discard) {
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builder->alpha_to_coverage = create_info->pMultisampleState->alphaToCoverageEnable;
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if (tu_blend_state_is_dual_src(create_info->pColorBlendState)) {
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builder->color_attachment_count++;
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builder->use_dual_src_blend = true;
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}
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}
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}
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