mirror of
https://gitlab.freedesktop.org/mesa/mesa.git
synced 2026-05-05 09:38:07 +02:00
radv: use ac_gpu_info
Reviewed-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Nicolai Hähnle
Dave Airlie
parent
eeb075d662
commit
bd4493b169
5 changed files with 13 additions and 229 deletions
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@ -769,7 +769,7 @@ static void radv_get_physical_device_queue_family_properties(
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{
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int num_queue_families = 1;
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int idx;
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if (pdevice->rad_info.compute_rings > 0 &&
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if (pdevice->rad_info.num_compute_rings > 0 &&
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pdevice->rad_info.chip_class >= CIK &&
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!(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
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num_queue_families++;
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@ -796,7 +796,7 @@ static void radv_get_physical_device_queue_family_properties(
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idx++;
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}
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if (pdevice->rad_info.compute_rings > 0 &&
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if (pdevice->rad_info.num_compute_rings > 0 &&
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pdevice->rad_info.chip_class >= CIK &&
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!(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
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if (*pCount > idx) {
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@ -804,7 +804,7 @@ static void radv_get_physical_device_queue_family_properties(
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.queueFlags = VK_QUEUE_COMPUTE_BIT |
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VK_QUEUE_TRANSFER_BIT |
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VK_QUEUE_SPARSE_BINDING_BIT,
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.queueCount = pdevice->rad_info.compute_rings,
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.queueCount = pdevice->rad_info.num_compute_rings,
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.timestampValidBits = 64,
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.minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
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};
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@ -888,11 +888,11 @@ void radv_GetPhysicalDeviceMemoryProperties(
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pMemoryProperties->memoryHeapCount = RADV_MEM_HEAP_COUNT;
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pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_VRAM] = (VkMemoryHeap) {
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.size = physical_device->rad_info.vram_size -
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physical_device->rad_info.visible_vram_size,
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physical_device->rad_info.vram_vis_size,
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.flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
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};
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pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_VRAM_CPU_ACCESS] = (VkMemoryHeap) {
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.size = physical_device->rad_info.visible_vram_size,
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.size = physical_device->rad_info.vram_vis_size,
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.flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
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};
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pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_GTT] = (VkMemoryHeap) {
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@ -53,6 +53,7 @@
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#include "radv_radeon_winsys.h"
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#include "ac_binary.h"
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#include "ac_nir_to_llvm.h"
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#include "ac_gpu_info.h"
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#include "ac_surface.h"
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#include "radv_debug.h"
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#include "radv_descriptor_set.h"
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@ -35,6 +35,7 @@
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#include "main/macros.h"
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#include "amd_family.h"
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struct radeon_info;
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struct ac_surf_info;
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struct radeon_surf;
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@ -74,60 +75,6 @@ struct radeon_winsys_cs {
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uint32_t *buf; /* The base pointer of the chunk. */
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};
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struct radeon_info {
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/* PCI info: domain:bus:dev:func */
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uint32_t pci_domain;
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uint32_t pci_bus;
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uint32_t pci_dev;
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uint32_t pci_func;
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/* Device info. */
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uint32_t pci_id;
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enum radeon_family family;
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enum chip_class chip_class;
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uint32_t gart_page_size;
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uint64_t gart_size;
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uint64_t vram_size;
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uint64_t visible_vram_size;
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bool has_dedicated_vram;
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bool has_virtual_memory;
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bool gfx_ib_pad_with_type2;
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bool has_uvd;
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uint32_t sdma_rings;
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uint32_t compute_rings;
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uint32_t vce_fw_version;
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uint32_t vce_harvest_config;
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uint32_t clock_crystal_freq; /* in kHz */
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/* Kernel info. */
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uint32_t drm_major; /* version */
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uint32_t drm_minor;
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uint32_t drm_patchlevel;
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bool has_userptr;
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/* Shader cores. */
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uint32_t r600_max_quad_pipes; /* wave size / 16 */
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uint32_t max_shader_clock;
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uint32_t num_good_compute_units;
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uint32_t max_se; /* shader engines */
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uint32_t max_sh_per_se; /* shader arrays per shader engine */
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/* Render backends (color + depth blocks). */
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uint32_t r300_num_gb_pipes;
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uint32_t r300_num_z_pipes;
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uint32_t r600_gb_backend_map; /* R600 harvest config */
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bool r600_gb_backend_map_valid;
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uint32_t r600_num_banks;
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uint32_t num_render_backends;
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uint32_t num_tile_pipes; /* pipe count from PIPE_CONFIG */
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uint32_t pipe_interleave_bytes;
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uint32_t enabled_rb_mask; /* GCN harvest config */
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/* Tile modes. */
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uint32_t si_tile_mode_array[32];
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uint32_t cik_macrotile_mode_array[16];
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};
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#define RADEON_SURF_TYPE_MASK 0xFF
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#define RADEON_SURF_TYPE_SHIFT 0
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#define RADEON_SURF_TYPE_1D 0
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@ -39,139 +39,14 @@
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#include "radv_amdgpu_bo.h"
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#include "radv_amdgpu_surface.h"
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#define CIK_TILE_MODE_COLOR_2D 14
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#define CIK__GB_TILE_MODE__PIPE_CONFIG(x) (((x) >> 6) & 0x1f)
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#define CIK__PIPE_CONFIG__ADDR_SURF_P2 0
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#define CIK__PIPE_CONFIG__ADDR_SURF_P4_8x16 4
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#define CIK__PIPE_CONFIG__ADDR_SURF_P4_16x16 5
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#define CIK__PIPE_CONFIG__ADDR_SURF_P4_16x32 6
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#define CIK__PIPE_CONFIG__ADDR_SURF_P4_32x32 7
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#define CIK__PIPE_CONFIG__ADDR_SURF_P8_16x16_8x16 8
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#define CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_8x16 9
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#define CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_8x16 10
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#define CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_16x16 11
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#define CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x16 12
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#define CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x32 13
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#define CIK__PIPE_CONFIG__ADDR_SURF_P8_32x64_32x32 14
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#define CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_8X16 16
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#define CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_16X16 17
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static unsigned radv_cik_get_num_tile_pipes(struct amdgpu_gpu_info *info)
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{
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unsigned mode2d = info->gb_tile_mode[CIK_TILE_MODE_COLOR_2D];
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switch (CIK__GB_TILE_MODE__PIPE_CONFIG(mode2d)) {
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case CIK__PIPE_CONFIG__ADDR_SURF_P2:
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return 2;
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case CIK__PIPE_CONFIG__ADDR_SURF_P4_8x16:
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case CIK__PIPE_CONFIG__ADDR_SURF_P4_16x16:
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case CIK__PIPE_CONFIG__ADDR_SURF_P4_16x32:
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case CIK__PIPE_CONFIG__ADDR_SURF_P4_32x32:
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return 4;
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case CIK__PIPE_CONFIG__ADDR_SURF_P8_16x16_8x16:
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case CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_8x16:
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case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_8x16:
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case CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_16x16:
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case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x16:
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case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x32:
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case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x64_32x32:
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return 8;
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case CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_8X16:
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case CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_16X16:
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return 16;
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default:
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fprintf(stderr, "Invalid CIK pipe configuration, assuming P2\n");
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assert(!"this should never occur");
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return 2;
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}
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}
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static bool
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do_winsys_init(struct radv_amdgpu_winsys *ws, int fd)
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{
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struct amdgpu_buffer_size_alignments alignment_info = {};
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struct amdgpu_heap_info vram, visible_vram, gtt;
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struct drm_amdgpu_info_hw_ip dma = {};
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struct drm_amdgpu_info_hw_ip compute = {};
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drmDevicePtr devinfo;
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int r;
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int i, j;
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/* Get PCI info. */
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r = drmGetDevice2(fd, 0, &devinfo);
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if (r) {
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fprintf(stderr, "amdgpu: drmGetDevice2 failed.\n");
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if (!ac_query_gpu_info(fd, ws->dev, &ws->info, &ws->amdinfo))
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goto fail;
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}
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ws->info.pci_domain = devinfo->businfo.pci->domain;
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ws->info.pci_bus = devinfo->businfo.pci->bus;
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ws->info.pci_dev = devinfo->businfo.pci->dev;
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ws->info.pci_func = devinfo->businfo.pci->func;
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drmFreeDevice(&devinfo);
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/* Query hardware and driver information. */
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r = amdgpu_query_gpu_info(ws->dev, &ws->amdinfo);
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if (r) {
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fprintf(stderr, "amdgpu: amdgpu_query_gpu_info failed.\n");
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goto fail;
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}
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r = amdgpu_query_buffer_size_alignment(ws->dev, &alignment_info);
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if (r) {
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fprintf(stderr, "amdgpu: amdgpu_query_buffer_size_alignment failed.\n");
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goto fail;
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}
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r = amdgpu_query_heap_info(ws->dev, AMDGPU_GEM_DOMAIN_VRAM, 0, &vram);
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if (r) {
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fprintf(stderr, "amdgpu: amdgpu_query_heap_info(vram) failed.\n");
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goto fail;
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}
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r = amdgpu_query_heap_info(ws->dev, AMDGPU_GEM_DOMAIN_VRAM,
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AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, &visible_vram);
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if (r) {
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fprintf(stderr, "amdgpu: amdgpu_query_heap_info(visible_vram) failed.\n");
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goto fail;
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}
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r = amdgpu_query_heap_info(ws->dev, AMDGPU_GEM_DOMAIN_GTT, 0, >t);
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if (r) {
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fprintf(stderr, "amdgpu: amdgpu_query_heap_info(gtt) failed.\n");
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goto fail;
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}
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r = amdgpu_query_hw_ip_info(ws->dev, AMDGPU_HW_IP_DMA, 0, &dma);
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if (r) {
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fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(dma) failed.\n");
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goto fail;
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}
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r = amdgpu_query_hw_ip_info(ws->dev, AMDGPU_HW_IP_COMPUTE, 0, &compute);
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if (r) {
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fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(compute) failed.\n");
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goto fail;
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}
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ws->info.pci_id = ws->amdinfo.asic_id; /* TODO: is this correct? */
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ws->info.vce_harvest_config = ws->amdinfo.vce_harvest_config;
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switch (ws->info.pci_id) {
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#define CHIPSET(pci_id, name, cfamily) case pci_id: ws->info.family = CHIP_##cfamily; break;
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#include "pci_ids/radeonsi_pci_ids.h"
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#undef CHIPSET
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default:
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fprintf(stderr, "amdgpu: Invalid PCI ID.\n");
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goto fail;
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}
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if (ws->info.family >= CHIP_TONGA)
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ws->info.chip_class = VI;
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else if (ws->info.family >= CHIP_BONAIRE)
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ws->info.chip_class = CIK;
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else if (ws->info.family >= CHIP_TAHITI)
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ws->info.chip_class = SI;
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else {
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fprintf(stderr, "amdgpu: Unknown family.\n");
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if (ws->info.chip_class >= GFX9) {
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fprintf(stderr, "radv: GFX9 is not supported.\n");
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goto fail;
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}
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@ -260,48 +135,8 @@ do_winsys_init(struct radv_amdgpu_winsys *ws, int fd)
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goto fail;
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}
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assert(util_is_power_of_two(dma.available_rings + 1));
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assert(util_is_power_of_two(compute.available_rings + 1));
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/* Set hardware information. */
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ws->info.gart_size = gtt.heap_size;
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ws->info.vram_size = vram.heap_size;
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ws->info.visible_vram_size = visible_vram.heap_size;
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/* convert the shader clock from KHz to MHz */
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ws->info.max_shader_clock = ws->amdinfo.max_engine_clk / 1000;
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ws->info.max_se = ws->amdinfo.num_shader_engines;
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ws->info.max_sh_per_se = ws->amdinfo.num_shader_arrays_per_engine;
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ws->info.has_uvd = 0;
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ws->info.vce_fw_version = 0;
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ws->info.has_userptr = TRUE;
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ws->info.num_render_backends = ws->amdinfo.rb_pipes;
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ws->info.clock_crystal_freq = ws->amdinfo.gpu_counter_freq;
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ws->info.num_tile_pipes = radv_cik_get_num_tile_pipes(&ws->amdinfo);
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ws->info.pipe_interleave_bytes = 256 << ((ws->amdinfo.gb_addr_cfg >> 4) & 0x7);
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ws->info.has_virtual_memory = TRUE;
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ws->info.sdma_rings = MIN2(util_bitcount(dma.available_rings),
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MAX_RINGS_PER_TYPE);
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ws->info.compute_rings = MIN2(util_bitcount(compute.available_rings),
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MAX_RINGS_PER_TYPE);
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/* Get the number of good compute units. */
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ws->info.num_good_compute_units = 0;
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for (i = 0; i < ws->info.max_se; i++)
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for (j = 0; j < ws->info.max_sh_per_se; j++)
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ws->info.num_good_compute_units +=
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util_bitcount(ws->amdinfo.cu_bitmap[i][j]);
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memcpy(ws->info.si_tile_mode_array, ws->amdinfo.gb_tile_mode,
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sizeof(ws->amdinfo.gb_tile_mode));
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ws->info.enabled_rb_mask = ws->amdinfo.enabled_rb_pipes_mask;
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memcpy(ws->info.cik_macrotile_mode_array, ws->amdinfo.gb_macro_tile_mode,
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sizeof(ws->amdinfo.gb_macro_tile_mode));
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ws->info.gart_page_size = alignment_info.size_remote;
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if (ws->info.chip_class == SI)
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ws->info.gfx_ib_pad_with_type2 = TRUE;
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ws->info.num_sdma_rings = MIN2(ws->info.num_sdma_rings, MAX_RINGS_PER_TYPE);
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ws->info.num_compute_rings = MIN2(ws->info.num_compute_rings, MAX_RINGS_PER_TYPE);
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ws->use_ib_bos = ws->family >= FAMILY_CI;
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return true;
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@ -29,6 +29,7 @@
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#define RADV_AMDGPU_WINSYS_H
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#include "radv_radeon_winsys.h"
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#include "ac_gpu_info.h"
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#include "addrlib/addrinterface.h"
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#include <amdgpu.h>
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#include "util/list.h"
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