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st/mesa: Treat vertex outputs absent in outputMapping as zero in mesa_to_tgsi

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After updating vertex outputs being written based on optimized NIR, they may
go out of sync with outputs in mesa IR. Which is translated to TGSI and used
together with NIR if draw doesn't have llvm.

It's much easier to treat such outputs as zero because there is no pass to
entirely get rid of them.

Similar to eeab9c93db but now for outputs.

Fixes: d684fb37bf
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3365
Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6187>
(cherry picked from commit 782ba8d3ae)
This commit is contained in:
Danylo Piliaiev 2020-08-05 18:07:06 +03:00 • committed by Eric Engestrom
parent 3dc4e3764f
commit bcf1a7a87d
2 changed files with 13 additions and 6 deletions
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2
.pick_status.json
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@ -4180,7 +4180,7 @@
"description": "st/mesa: Treat vertex outputs absent in outputMapping as zero in mesa_to_tgsi",
"nominated": true,
"nomination_type": 1,
"resolution": 0,
"resolution": 1,
"master_sha": null,
"because_sha": "d684fb37bfbc47d098158cb03c0672119a4469fe"
},

17
src/mesa/state_tracker/st_mesa_to_tgsi.c
View file

@ -97,9 +97,12 @@ dst_register(struct st_translate *t, gl_register_file file, GLuint index)
else
assert(index < VARYING_SLOT_MAX);
assert(t->outputMapping[index] < ARRAY_SIZE(t->outputs));
return t->outputs[t->outputMapping[index]];
if (t->outputMapping[index] < ARRAY_SIZE(t->outputs))
return t->outputs[t->outputMapping[index]];
else {
assert(t->procType == PIPE_SHADER_VERTEX);
return ureg_dst(ureg_DECL_constant(t->ureg, 0));
}
case PROGRAM_ADDRESS:
return t->address[index];
@ -149,8 +152,12 @@ src_register(struct st_translate *t,
}
case PROGRAM_OUTPUT:
assert(t->outputMapping[index] < ARRAY_SIZE(t->outputs));
return ureg_src(t->outputs[t->outputMapping[index]]); /* not needed? */
if (t->outputMapping[index] < ARRAY_SIZE(t->outputs))
return ureg_src(t->outputs[t->outputMapping[index]]);
else {
assert(t->procType == PIPE_SHADER_VERTEX);
return ureg_DECL_constant(t->ureg, 0);
}
case PROGRAM_ADDRESS:
return ureg_src(t->address[index]);