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radv: Expose function to write vertex descriptors for dgc.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17269>
This commit is contained in:
Bas Nieuwenhuizen
Marge Bot
parent
82c2e99102
commit
bce3af2cb3
2 changed files with 141 additions and 131 deletions
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@ -3424,6 +3424,142 @@ static const uint32_t data_format_dst_sel[] = {
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[V_008F0C_BUF_DATA_FORMAT_32_32_32_32] = DST_SEL_XYZW,
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};
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void
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radv_write_vertex_descriptors(const struct radv_cmd_buffer *cmd_buffer,
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const struct radv_graphics_pipeline *pipeline, void *vb_ptr)
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{
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struct radv_shader *vs_shader = radv_get_shader(&pipeline->base, MESA_SHADER_VERTEX);
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enum amd_gfx_level chip = cmd_buffer->device->physical_device->rad_info.gfx_level;
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unsigned desc_index = 0;
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uint32_t mask = pipeline->vb_desc_usage_mask;
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uint64_t va;
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const struct radv_vs_input_state *vs_state =
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vs_shader->info.vs.dynamic_inputs ? &cmd_buffer->state.dynamic_vs_input : NULL;
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assert(!vs_state || pipeline->use_per_attribute_vb_descs);
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while (mask) {
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unsigned i = u_bit_scan(&mask);
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uint32_t *desc = &((uint32_t *)vb_ptr)[desc_index++ * 4];
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uint32_t offset, rsrc_word3;
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unsigned binding =
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vs_state ? cmd_buffer->state.dynamic_vs_input.bindings[i]
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: (pipeline->use_per_attribute_vb_descs ? pipeline->attrib_bindings[i] : i);
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struct radv_buffer *buffer = cmd_buffer->vertex_binding_buffers[binding];
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unsigned num_records;
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unsigned stride;
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if (vs_state) {
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unsigned format = vs_state->formats[i];
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unsigned dfmt = format & 0xf;
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unsigned nfmt = (format >> 4) & 0x7;
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rsrc_word3 = vs_state->post_shuffle & (1u << i) ? DST_SEL_ZYXW : data_format_dst_sel[dfmt];
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if (chip >= GFX10)
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rsrc_word3 |= S_008F0C_FORMAT(ac_get_tbuffer_format(chip, dfmt, nfmt));
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else
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rsrc_word3 |= S_008F0C_NUM_FORMAT(nfmt) | S_008F0C_DATA_FORMAT(dfmt);
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} else {
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if (chip >= GFX10)
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rsrc_word3 = DST_SEL_XYZW | S_008F0C_FORMAT(V_008F0C_GFX10_FORMAT_32_UINT);
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else
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rsrc_word3 = DST_SEL_XYZW | S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_UINT) |
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S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
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}
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if (!buffer) {
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if (vs_state) {
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/* Stride needs to be non-zero on GFX9, or else bounds checking is disabled. We need
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* to include the format/word3 so that the alpha channel is 1 for formats without an
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* alpha channel.
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*/
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desc[0] = 0;
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desc[1] = S_008F04_STRIDE(16);
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desc[2] = 0;
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desc[3] = rsrc_word3;
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} else {
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memset(desc, 0, 4 * 4);
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}
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continue;
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}
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va = radv_buffer_get_va(buffer->bo);
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offset = cmd_buffer->vertex_bindings[binding].offset;
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va += offset + buffer->offset;
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if (vs_state)
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va += vs_state->offsets[i];
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if (cmd_buffer->vertex_bindings[binding].size) {
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num_records = cmd_buffer->vertex_bindings[binding].size;
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} else {
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num_records = vk_buffer_range(&buffer->vk, offset, VK_WHOLE_SIZE);
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}
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if (pipeline->uses_dynamic_stride) {
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stride = cmd_buffer->vertex_bindings[binding].stride;
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} else {
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stride = pipeline->binding_stride[binding];
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}
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if (pipeline->use_per_attribute_vb_descs) {
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uint32_t attrib_end =
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vs_state ? vs_state->offsets[i] + vs_state->format_sizes[i] : pipeline->attrib_ends[i];
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if (num_records < attrib_end) {
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num_records = 0; /* not enough space for one vertex */
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} else if (stride == 0) {
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num_records = 1; /* only one vertex */
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} else {
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num_records = (num_records - attrib_end) / stride + 1;
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/* If attrib_offset>stride, then the compiler will increase the vertex index by
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* attrib_offset/stride and decrease the offset by attrib_offset%stride. This is
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* only allowed with static strides.
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*/
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num_records += pipeline->attrib_index_offset[i];
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}
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/* GFX10 uses OOB_SELECT_RAW if stride==0, so convert num_records from elements into
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* into bytes in that case. GFX8 always uses bytes.
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*/
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if (num_records && (chip == GFX8 || (chip != GFX9 && !stride))) {
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num_records = (num_records - 1) * stride + attrib_end;
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} else if (!num_records) {
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/* On GFX9, it seems bounds checking is disabled if both
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* num_records and stride are zero. This doesn't seem necessary on GFX8, GFX10 and
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* GFX10.3 but it doesn't hurt.
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*/
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if (vs_state) {
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desc[0] = 0;
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desc[1] = S_008F04_STRIDE(16);
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desc[2] = 0;
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desc[3] = rsrc_word3;
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} else {
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memset(desc, 0, 16);
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}
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continue;
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}
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} else {
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if (chip != GFX8 && stride)
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num_records = DIV_ROUND_UP(num_records, stride);
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}
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if (chip >= GFX10) {
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/* OOB_SELECT chooses the out-of-bounds check:
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* - 1: index >= NUM_RECORDS (Structured)
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* - 3: offset >= NUM_RECORDS (Raw)
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*/
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int oob_select = stride ? V_008F0C_OOB_SELECT_STRUCTURED : V_008F0C_OOB_SELECT_RAW;
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rsrc_word3 |= S_008F0C_OOB_SELECT(oob_select) | S_008F0C_RESOURCE_LEVEL(chip < GFX11);
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}
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desc[0] = va;
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desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
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desc[2] = num_records;
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desc[3] = rsrc_word3;
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}
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}
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static void
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radv_flush_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
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{
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@ -3433,144 +3569,16 @@ radv_flush_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_
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assert(!cmd_buffer->state.mesh_shading);
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struct radv_graphics_pipeline *pipeline = cmd_buffer->state.graphics_pipeline;
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struct radv_shader *vs_shader = radv_get_shader(&pipeline->base, MESA_SHADER_VERTEX);
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enum amd_gfx_level chip = cmd_buffer->device->physical_device->rad_info.gfx_level;
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unsigned vb_offset;
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void *vb_ptr;
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unsigned desc_index = 0;
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uint32_t mask = pipeline->vb_desc_usage_mask;
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uint64_t va;
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const struct radv_vs_input_state *vs_state =
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vs_shader->info.vs.dynamic_inputs ? &cmd_buffer->state.dynamic_vs_input : NULL;
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/* allocate some descriptor state for vertex buffers */
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if (!radv_cmd_buffer_upload_alloc(cmd_buffer, pipeline->vb_desc_alloc_size, &vb_offset, &vb_ptr))
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if (!radv_cmd_buffer_upload_alloc(cmd_buffer, pipeline->vb_desc_alloc_size, &vb_offset,
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&vb_ptr))
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return;
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assert(!vs_state || pipeline->use_per_attribute_vb_descs);
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while (mask) {
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unsigned i = u_bit_scan(&mask);
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uint32_t *desc = &((uint32_t *)vb_ptr)[desc_index++ * 4];
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uint32_t offset, rsrc_word3;
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unsigned binding =
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vs_state ? cmd_buffer->state.dynamic_vs_input.bindings[i]
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: (pipeline->use_per_attribute_vb_descs ? pipeline->attrib_bindings[i] : i);
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struct radv_buffer *buffer = cmd_buffer->vertex_binding_buffers[binding];
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unsigned num_records;
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unsigned stride;
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if (vs_state) {
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unsigned format = vs_state->formats[i];
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unsigned dfmt = format & 0xf;
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unsigned nfmt = (format >> 4) & 0x7;
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rsrc_word3 =
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vs_state->post_shuffle & (1u << i) ? DST_SEL_ZYXW : data_format_dst_sel[dfmt];
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if (chip >= GFX10)
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rsrc_word3 |= S_008F0C_FORMAT(ac_get_tbuffer_format(chip, dfmt, nfmt));
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else
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rsrc_word3 |= S_008F0C_NUM_FORMAT(nfmt) | S_008F0C_DATA_FORMAT(dfmt);
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} else {
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if (chip >= GFX10)
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rsrc_word3 = DST_SEL_XYZW | S_008F0C_FORMAT(V_008F0C_GFX10_FORMAT_32_UINT);
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else
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rsrc_word3 = DST_SEL_XYZW | S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_UINT) |
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S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
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}
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if (!buffer) {
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if (vs_state) {
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/* Stride needs to be non-zero on GFX9, or else bounds checking is disabled. We need
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* to include the format/word3 so that the alpha channel is 1 for formats without an
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* alpha channel.
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*/
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desc[0] = 0;
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desc[1] = S_008F04_STRIDE(16);
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desc[2] = 0;
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desc[3] = rsrc_word3;
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} else {
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memset(desc, 0, 4 * 4);
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}
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continue;
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}
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va = radv_buffer_get_va(buffer->bo);
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offset = cmd_buffer->vertex_bindings[binding].offset;
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va += offset + buffer->offset;
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if (vs_state)
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va += vs_state->offsets[i];
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if (cmd_buffer->vertex_bindings[binding].size) {
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num_records = cmd_buffer->vertex_bindings[binding].size;
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} else {
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num_records = vk_buffer_range(&buffer->vk, offset, VK_WHOLE_SIZE);
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}
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if (pipeline->uses_dynamic_stride) {
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stride = cmd_buffer->vertex_bindings[binding].stride;
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} else {
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stride = pipeline->binding_stride[binding];
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}
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if (pipeline->use_per_attribute_vb_descs) {
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uint32_t attrib_end = vs_state ? vs_state->offsets[i] + vs_state->format_sizes[i]
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: pipeline->attrib_ends[i];
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if (num_records < attrib_end) {
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num_records = 0; /* not enough space for one vertex */
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} else if (stride == 0) {
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num_records = 1; /* only one vertex */
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} else {
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num_records = (num_records - attrib_end) / stride + 1;
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/* If attrib_offset>stride, then the compiler will increase the vertex index by
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* attrib_offset/stride and decrease the offset by attrib_offset%stride. This is
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* only allowed with static strides.
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*/
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num_records += pipeline->attrib_index_offset[i];
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}
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/* GFX10 uses OOB_SELECT_RAW if stride==0, so convert num_records from elements into
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* into bytes in that case. GFX8 always uses bytes.
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*/
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if (num_records && (chip == GFX8 || (chip != GFX9 && !stride))) {
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num_records = (num_records - 1) * stride + attrib_end;
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} else if (!num_records) {
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/* On GFX9, it seems bounds checking is disabled if both
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* num_records and stride are zero. This doesn't seem necessary on GFX8, GFX10 and
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* GFX10.3 but it doesn't hurt.
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*/
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if (vs_state) {
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desc[0] = 0;
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desc[1] = S_008F04_STRIDE(16);
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desc[2] = 0;
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desc[3] = rsrc_word3;
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} else {
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memset(desc, 0, 16);
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}
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continue;
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}
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} else {
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if (chip != GFX8 && stride)
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num_records = DIV_ROUND_UP(num_records, stride);
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}
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if (chip >= GFX10) {
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/* OOB_SELECT chooses the out-of-bounds check:
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* - 1: index >= NUM_RECORDS (Structured)
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* - 3: offset >= NUM_RECORDS (Raw)
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*/
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int oob_select = stride ? V_008F0C_OOB_SELECT_STRUCTURED : V_008F0C_OOB_SELECT_RAW;
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rsrc_word3 |= S_008F0C_OOB_SELECT(oob_select) | S_008F0C_RESOURCE_LEVEL(chip < GFX11);
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}
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desc[0] = va;
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desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
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desc[2] = num_records;
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desc[3] = rsrc_word3;
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}
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radv_write_vertex_descriptors(cmd_buffer, pipeline, vb_ptr);
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va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
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va += vb_offset;
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@ -1691,6 +1691,8 @@ void radv_cmd_buffer_restore_subpass(struct radv_cmd_buffer *cmd_buffer,
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const struct radv_subpass *subpass);
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bool radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer, unsigned size,
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const void *data, unsigned *out_offset);
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void radv_write_vertex_descriptors(const struct radv_cmd_buffer *cmd_buffer,
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const struct radv_graphics_pipeline *pipeline, void *vb_ptr);
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void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer);
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void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer);
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