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anv: implement gen12 post sync pipe control workaround

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Same as Skylake.

v2: Restrict to A0

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3405>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3405>
This commit is contained in:
Lionel Landwerlin 2020-01-15 14:09:26 +02:00 • committed by Marge Bot
parent 8949d27bb8
commit bcb611361b
1 changed files with 5 additions and 1 deletions
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6
src/intel/vulkan/genX_cmd_buffer.c
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@ -1993,6 +1993,7 @@ genX(cmd_buffer_config_l3)(struct anv_cmd_buffer *cmd_buffer,
void void
genX(cmd_buffer_apply_pipe_flushes)(struct anv_cmd_buffer *cmd_buffer) genX(cmd_buffer_apply_pipe_flushes)(struct anv_cmd_buffer *cmd_buffer)
{ {
UNUSED const struct gen_device_info *devinfo = &cmd_buffer->device->info;
enum anv_pipe_bits bits = cmd_buffer->state.pending_pipe_bits; enum anv_pipe_bits bits = cmd_buffer->state.pending_pipe_bits;
if (cmd_buffer->device->physical->always_flush_cache) if (cmd_buffer->device->physical->always_flush_cache)
@ -2058,9 +2059,12 @@ genX(cmd_buffer_apply_pipe_flushes)(struct anv_cmd_buffer *cmd_buffer)
* PIPELINE_SELECT command is set to GPGPU mode of operation)." * PIPELINE_SELECT command is set to GPGPU mode of operation)."
* *
* The same text exists a few rows below for Post Sync Op. * The same text exists a few rows below for Post Sync Op.
*
* On Gen12 this is GEN:BUG:1607156449.
*/ */
if (bits & ANV_PIPE_POST_SYNC_BIT) { if (bits & ANV_PIPE_POST_SYNC_BIT) {
if (GEN_GEN == 9 && cmd_buffer->state.current_pipeline == GPGPU) if ((GEN_GEN == 9 || (GEN_GEN == 12 && devinfo->revision == 0 /* A0 */)) &&
cmd_buffer->state.current_pipeline == GPGPU)
bits |= ANV_PIPE_CS_STALL_BIT; bits |= ANV_PIPE_CS_STALL_BIT;
bits &= ~ANV_PIPE_POST_SYNC_BIT; bits &= ~ANV_PIPE_POST_SYNC_BIT;
} }