radv: rename NGG culling user SGPRs

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37022>
This commit is contained in:
Samuel Pitoiset 2025-08-29 08:27:35 +02:00 committed by Marge Bot
parent b35bb9f5c7
commit bc9a020dd3
4 changed files with 24 additions and 24 deletions

View file

@ -40,7 +40,7 @@ load_ring(nir_builder *b, unsigned ring, lower_abi_state *s)
static nir_def *
nggc_bool_setting(nir_builder *b, unsigned mask, lower_abi_state *s)
{
nir_def *settings = ac_nir_load_arg(b, &s->args->ac, s->args->ngg_culling_settings);
nir_def *settings = ac_nir_load_arg(b, &s->args->ac, s->args->nggc_settings);
return nir_test_mask(b, settings, mask);
}
@ -173,7 +173,7 @@ lower_abi_instr(nir_builder *b, nir_intrinsic_instr *intrin, void *state)
nir_def *mask =
nir_bcsel(b, small_workgroup, nir_imm_int(b, radv_nggc_none),
nir_imm_int(b, radv_nggc_front_face | radv_nggc_back_face | radv_nggc_small_primitives));
nir_def *settings = ac_nir_load_arg(b, &s->args->ac, s->args->ngg_culling_settings);
nir_def *settings = ac_nir_load_arg(b, &s->args->ac, s->args->nggc_settings);
replacement = nir_ine_imm(b, nir_iand(b, settings, mask), 0);
break;
}
@ -195,7 +195,7 @@ lower_abi_instr(nir_builder *b, nir_intrinsic_instr *intrin, void *state)
* exponent = nggc_settings >> 24
* precision = 1.0 * 2 ^ exponent
*/
nir_def *settings = ac_nir_load_arg(b, &s->args->ac, s->args->ngg_culling_settings);
nir_def *settings = ac_nir_load_arg(b, &s->args->ac, s->args->nggc_settings);
nir_def *exponent = nir_ishr_imm(b, settings, 24u);
replacement = nir_ldexp(b, nir_imm_float(b, 1.0f), exponent);
break;
@ -203,10 +203,10 @@ lower_abi_instr(nir_builder *b, nir_intrinsic_instr *intrin, void *state)
case nir_intrinsic_load_cull_triangle_viewport_xy_scale_and_offset_amd: {
nir_def *comps[] = {
ac_nir_load_arg(b, &s->args->ac, s->args->ngg_viewport_scale[0]),
ac_nir_load_arg(b, &s->args->ac, s->args->ngg_viewport_scale[1]),
ac_nir_load_arg(b, &s->args->ac, s->args->ngg_viewport_translate[0]),
ac_nir_load_arg(b, &s->args->ac, s->args->ngg_viewport_translate[1]),
ac_nir_load_arg(b, &s->args->ac, s->args->nggc_viewport_scale[0]),
ac_nir_load_arg(b, &s->args->ac, s->args->nggc_viewport_scale[1]),
ac_nir_load_arg(b, &s->args->ac, s->args->nggc_viewport_translate[0]),
ac_nir_load_arg(b, &s->args->ac, s->args->nggc_viewport_translate[1]),
};
replacement = nir_vec(b, comps, 4);
break;

View file

@ -10825,7 +10825,7 @@ radv_need_late_scissor_emission(struct radv_cmd_buffer *cmd_buffer, const struct
}
ALWAYS_INLINE static uint32_t
radv_get_ngg_culling_settings(struct radv_cmd_buffer *cmd_buffer, bool vp_y_inverted)
radv_get_nggc_settings(struct radv_cmd_buffer *cmd_buffer, bool vp_y_inverted)
{
const struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
@ -10897,7 +10897,7 @@ radv_emit_ngg_culling_state(struct radv_cmd_buffer *cmd_buffer)
bool vp_y_inverted = (-vp_scale[1] + vp_translate[1]) > (vp_scale[1] + vp_translate[1]);
/* Get current culling settings. */
uint32_t nggc_settings = radv_get_ngg_culling_settings(cmd_buffer, vp_y_inverted);
uint32_t nggc_settings = radv_get_nggc_settings(cmd_buffer, vp_y_inverted);
radeon_begin(cmd_buffer->cs);
@ -10917,15 +10917,15 @@ radv_emit_ngg_culling_state(struct radv_cmd_buffer *cmd_buffer)
}
uint32_t vp_reg_values[4] = {fui(vp_scale[0]), fui(vp_scale[1]), fui(vp_translate[0]), fui(vp_translate[1])};
const uint32_t ngg_viewport_offset = radv_get_user_sgpr_loc(last_vgt_shader, AC_UD_NGG_VIEWPORT);
const uint32_t nggc_viewport_offset = radv_get_user_sgpr_loc(last_vgt_shader, AC_UD_NGGC_VIEWPORT);
radeon_set_sh_reg_seq(ngg_viewport_offset, 4);
radeon_set_sh_reg_seq(nggc_viewport_offset, 4);
radeon_emit_array(vp_reg_values, 4);
}
const uint32_t ngg_culling_settings_offset = radv_get_user_sgpr_loc(last_vgt_shader, AC_UD_NGG_CULLING_SETTINGS);
const uint32_t nggc_settings_offset = radv_get_user_sgpr_loc(last_vgt_shader, AC_UD_NGGC_SETTINGS);
radeon_set_sh_reg(ngg_culling_settings_offset, nggc_settings);
radeon_set_sh_reg(nggc_settings_offset, nggc_settings);
radeon_end();
}

View file

@ -291,11 +291,11 @@ declare_ngg_sgprs(const struct radv_shader_info *info, struct radv_shader_args *
add_ud_arg(args, 1, AC_ARG_VALUE, &args->ngg_state, AC_UD_NGG_STATE);
if (info->has_ngg_culling) {
add_ud_arg(args, 1, AC_ARG_VALUE, &args->ngg_culling_settings, AC_UD_NGG_CULLING_SETTINGS);
add_ud_arg(args, 1, AC_ARG_VALUE, &args->ngg_viewport_scale[0], AC_UD_NGG_VIEWPORT);
add_ud_arg(args, 1, AC_ARG_VALUE, &args->ngg_viewport_scale[1], AC_UD_NGG_VIEWPORT);
add_ud_arg(args, 1, AC_ARG_VALUE, &args->ngg_viewport_translate[0], AC_UD_NGG_VIEWPORT);
add_ud_arg(args, 1, AC_ARG_VALUE, &args->ngg_viewport_translate[1], AC_UD_NGG_VIEWPORT);
add_ud_arg(args, 1, AC_ARG_VALUE, &args->nggc_settings, AC_UD_NGGC_SETTINGS);
add_ud_arg(args, 1, AC_ARG_VALUE, &args->nggc_viewport_scale[0], AC_UD_NGGC_VIEWPORT);
add_ud_arg(args, 1, AC_ARG_VALUE, &args->nggc_viewport_scale[1], AC_UD_NGGC_VIEWPORT);
add_ud_arg(args, 1, AC_ARG_VALUE, &args->nggc_viewport_translate[0], AC_UD_NGGC_VIEWPORT);
add_ud_arg(args, 1, AC_ARG_VALUE, &args->nggc_viewport_translate[1], AC_UD_NGGC_VIEWPORT);
}
}

View file

@ -23,8 +23,8 @@ enum radv_ud_index {
AC_UD_STREAMOUT_BUFFERS = 5,
AC_UD_STREAMOUT_STATE = 6,
AC_UD_TASK_STATE = 7,
AC_UD_NGG_CULLING_SETTINGS = 8,
AC_UD_NGG_VIEWPORT = 9,
AC_UD_NGGC_SETTINGS = 8,
AC_UD_NGGC_VIEWPORT = 9,
AC_UD_NGG_LDS_LAYOUT = 10,
AC_UD_NGG_STATE = 11,
AC_UD_NGG_QUERY_BUF_VA = 12,
@ -89,10 +89,10 @@ struct radv_shader_args {
struct ac_arg ngg_lds_layout;
struct ac_arg ngg_query_buf_va; /* GFX11+ */
/* NGG GS */
struct ac_arg ngg_culling_settings;
struct ac_arg ngg_viewport_scale[2];
struct ac_arg ngg_viewport_translate[2];
/* NGG Culling */
struct ac_arg nggc_settings;
struct ac_arg nggc_viewport_scale[2];
struct ac_arg nggc_viewport_translate[2];
/* Fragment shaders */
struct ac_arg ps_state;