diff --git a/src/amd/compiler/aco_instruction_selection.cpp b/src/amd/compiler/aco_instruction_selection.cpp
index bd9eff72647..faddfee3c04 100644
--- a/src/amd/compiler/aco_instruction_selection.cpp
+++ b/src/amd/compiler/aco_instruction_selection.cpp
@@ -10847,8 +10847,9 @@ create_vs_exports(isel_context* ctx)
    int next_pos = 0;
    export_vs_varying(ctx, VARYING_SLOT_POS, true, &next_pos);
 
+   bool force_vrs_per_vertex = ctx->options->force_vrs_rates && ctx->stage != mesh_ngg;
    bool writes_primitive_shading_rate =
-      outinfo->writes_primitive_shading_rate || ctx->options->force_vrs_rates;
+      outinfo->writes_primitive_shading_rate || force_vrs_per_vertex;
    if (outinfo->writes_pointsize || outinfo->writes_layer || outinfo->writes_viewport_index ||
        writes_primitive_shading_rate) {
       export_vs_psiz_layer_viewport_vrs(ctx, &next_pos, outinfo);
@@ -10916,6 +10917,11 @@ create_primitive_exports(isel_context *ctx, Temp prim_ch1)
       Temp tmp = ctx->outputs.temps[VARYING_SLOT_VIEWPORT * 4u];
       ch2 = bld.vop3(aco_opcode::v_lshl_or_b32, bld.def(v1), tmp, Operand::c32(20), ch2);
    }
+   if (outinfo->writes_primitive_shading_rate_per_primitive) {
+      en_mask |= 2;
+      Temp tmp = ctx->outputs.temps[VARYING_SLOT_PRIMITIVE_SHADING_RATE * 4u];
+      ch2 = bld.vop2(aco_opcode::v_or_b32, bld.def(v1), tmp, ch2);
+   }
 
    Operand prim_ch2 = (en_mask & 2) ? Operand(ch2) : Operand(v1);
 
@@ -10927,6 +10933,8 @@ create_primitive_exports(isel_context *ctx, Temp prim_ch1)
    for (unsigned i = 0; i <= VARYING_SLOT_VAR31; ++i) {
       if (!(ctx->shader->info.per_primitive_outputs & BITFIELD64_BIT(i)))
          continue;
+      if (i == VARYING_SLOT_PRIMITIVE_SHADING_RATE)
+         continue;
 
       export_vs_varying(ctx, i, false, NULL);
    }