From bc8e29c04e2c900e5f863a50a85d2476ff104819 Mon Sep 17 00:00:00 2001 From: Sagar Ghuge Date: Mon, 1 Sep 2025 14:19:24 -0700 Subject: [PATCH] iris: Emit state cache invalidation after every compute dispatch MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Implement HSD 16028171704/14025112257: LSC state cache livelock:- Once state cache entries are full, subsequent walker dispatches with two threads per thread group maybe gets stuck infinitely because of state cache live lock. One thread continuously stuck in loop doing UGM fence + evict and UGM read is waiting on UGM read to have certain value. while other thread supposed to update the value that first thread is waiting for. But since entries are full in state cache, there is second thread never make progress. Closes: #12352 Signed-off-by: Sagar Ghuge Reviewed-by: Tapani Pälli Part-of: --- src/gallium/drivers/iris/iris_state.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c index 55ecf449e8f..137fcd99073 100644 --- a/src/gallium/drivers/iris/iris_state.c +++ b/src/gallium/drivers/iris/iris_state.c @@ -668,6 +668,15 @@ iris_rewrite_compute_walker_pc(struct iris_batch *batch, for (uint32_t i = 0; i < GENX(COMPUTE_WALKER_length); i++) walker[i] |= dwords[i]; + + /* + * TDOD: Add INTEL_NEEDS_WA_14025112257 check once HSD is propogated for all + * other impacted platforms. + */ + if (screen->devinfo->ver >= 20 && batch->name == IRIS_BATCH_COMPUTE) { + iris_emit_pipe_control_flush(batch, "WA_14025112257", + PIPE_CONTROL_STATE_CACHE_INVALIDATE); + } #else UNREACHABLE("Unsupported"); #endif @@ -9250,6 +9259,15 @@ iris_upload_compute_walker(struct iris_context *ice, } } + /* + * TDOD: Add INTEL_NEEDS_WA_14025112257 check once HSD is propogated for all + * other impacted platforms. + */ + if (screen->devinfo->ver >= 20 && batch->name == IRIS_BATCH_COMPUTE) { + iris_emit_pipe_control_flush(batch, "WA_14025112257", + PIPE_CONTROL_STATE_CACHE_INVALIDATE); + } + trace_intel_end_compute(&batch->trace, grid->grid[0], grid->grid[1], grid->grid[2], 0); }