fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-05-05 00:58:05 +02:00
Code Issues Projects Releases Packages Wiki Activity Actions 2

ir3: Add ldg.k instruction

Browse source 
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26934>
This commit is contained in:
Danylo Piliaiev 2023-12-01 17:14:14 +01:00 • committed by Marge Bot
parent ad52f92cb8
commit bc6b847017
7 changed files with 78 additions and 34 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

1
src/freedreno/ir3/disasm-a3xx.c
View file

@ -400,6 +400,7 @@ static const struct opc_info {
OPC(6, OPC_STC, stc),
OPC(6, OPC_STSC, stsc),
OPC(6, OPC_LDC_K, ldc.k),
OPC(6, OPC_LDG_K, ldg.k),
OPC(6, OPC_SPILL_MACRO, spill.macro),
OPC(6, OPC_RELOAD_MACRO, reload.macro),

1
src/freedreno/ir3/instr-a3xx.h
View file

@ -364,6 +364,7 @@ typedef enum {
OPC_LDC_K = _OPC(6, 81),
OPC_STSC = _OPC(6, 82),
OPC_LDG_K = _OPC(6, 83),
/* category 7: */
OPC_BAR = _OPC(7, 0),

1
src/freedreno/ir3/ir3_lexer.l
View file

@ -309,6 +309,7 @@ static int parse_reg(const char *str)
/* category 6: */
"ldg" return TOKEN(T_OP_LDG);
"ldg.a" return TOKEN(T_OP_LDG_A);
"ldg.k" return TOKEN(T_OP_LDG_K);
"ldl" return TOKEN(T_OP_LDL);
"ldp" return TOKEN(T_OP_LDP);
"stg" return TOKEN(T_OP_STG);

8
src/freedreno/ir3/ir3_parser.y
View file

@ -558,6 +558,7 @@ static void print_token(FILE *file, int type, YYSTYPE value)
/* category 6: */
%token <tok> T_OP_LDG
%token <tok> T_OP_LDG_A
%token <tok> T_OP_LDG_K
%token <tok> T_OP_LDL
%token <tok> T_OP_LDP
%token <tok> T_OP_STG
@ -1170,6 +1171,7 @@ cat6_a6xx_global_address:
cat6_load: T_OP_LDG { new_instr(OPC_LDG); } cat6_type dst_reg ',' 'g' '[' src cat6_offset ']' ',' immediate
| T_OP_LDG_A { new_instr(OPC_LDG_A); } cat6_type dst_reg ',' 'g' '[' cat6_a6xx_global_address ']' ',' immediate
| T_OP_LDG_K { new_instr(OPC_LDG_K); } cat6_type 'c' '[' const_dst ']' ',' 'g' '[' src cat6_offset ']' ',' immediate
| T_OP_LDP { new_instr(OPC_LDP); } cat6_type dst_reg ',' 'p' '[' src cat6_offset ']' ',' immediate
| T_OP_LDL { new_instr(OPC_LDL); } cat6_type dst_reg ',' 'l' '[' src cat6_offset ']' ',' immediate
| T_OP_LDLW { new_instr(OPC_LDLW); } cat6_type dst_reg ',' 'l' '[' src cat6_offset ']' ',' immediate
@ -1294,13 +1296,13 @@ cat6_bindless_ldc: cat6_bindless_ldc_opc '.' cat6_bindless_ldc_middle ',' cat6_r
swap(instr->srcs[0], instr->srcs[1]);
}
stc_dst: integer { new_src(0, IR3_REG_IMMED)->iim_val = $1; }
const_dst: integer { new_src(0, IR3_REG_IMMED)->iim_val = $1; }
| T_A1 { new_src(0, IR3_REG_IMMED)->iim_val = 0; instr->flags |= IR3_INSTR_A1EN; }
| T_A1 '+' integer { new_src(0, IR3_REG_IMMED)->iim_val = $3; instr->flags |= IR3_INSTR_A1EN; }
cat6_stc:
T_OP_STC { new_instr(OPC_STC); } cat6_type 'c' '[' stc_dst ']' ',' src_reg ',' cat6_immed
| T_OP_STSC { new_instr(OPC_STSC); } cat6_type 'c' '[' stc_dst ']' ',' immediate ',' cat6_immed
T_OP_STC { new_instr(OPC_STC); } cat6_type 'c' '[' const_dst ']' ',' src_reg ',' cat6_immed
| T_OP_STSC { new_instr(OPC_STSC); } cat6_type 'c' '[' const_dst ']' ',' immediate ',' cat6_immed
cat6_todo: T_OP_G2L { new_instr(OPC_G2L); }
| T_OP_L2G { new_instr(OPC_L2G); }

3
src/freedreno/ir3/tests/disasm.c
View file

@ -393,6 +393,9 @@ static const struct test {
/* Custom stp based on above to catch a disasm bug. */
INSTR_6XX(c1465b00_0180022a, "stp.u32 p[r11.y+256], r5.y, 1"),
INSTR_6XX(c0160010_00b001a1, "ldg.k.u32 c[16], g[r48.x+208], 1"),
INSTR_6XX(c0160188_00b01261, "ldg.k.u32 c[a1.x+136], g[r48.x+2352], 1"),
/* Atomic: */
#if 0
/* TODO our encoding differs in b53 for these two */

8
src/freedreno/isa/encode.c
View file

@ -309,14 +309,14 @@ __cat3_src_case(struct encode_state *s, struct ir3_register *reg)
}
typedef enum {
STC_DST_IMM,
STC_DST_A1
CONST_DST_IMM,
CONST_DST_A1
} stc_dst_t;
static inline stc_dst_t
__stc_dst_case(struct encode_state *s, struct ir3_instruction *instr)
__const_dst_case(struct encode_state *s, struct ir3_instruction *instr)
{
return (instr->flags & IR3_INSTR_A1EN) ? STC_DST_A1 : STC_DST_IMM;
return (instr->flags & IR3_INSTR_A1EN) ? CONST_DST_A1 : CONST_DST_IMM;
}
#include "encode.h"

90
src/freedreno/isa/ir3-cat6.xml
View file

@ -34,8 +34,35 @@ SOFTWARE.
'.b' - "bindless" instructions
'.g' - "global" atomics that operate on raw iova addresses
'.s' - "ssbo" pre-a6xx image/ssbo atomics
'.k' - "constants" load into constant reg file
-->
<bitset name="#const-dst-imm" extends="#const-dst">
<display>
{OFFSET}
</display>
<field name="OFFSET" low="0" high="7" type="uint"/>
<pattern pos="8">0</pattern>
</bitset>
<bitset name="#const-dst-a1" extends="#const-dst">
<display>
a1.x{OFFSET}
</display>
<field name="OFFSET" low="0" high="7" type="uoffset"/>
<pattern pos="8">1</pattern>
</bitset>
<bitset name="#const-dst" size="9">
<doc>
Encoding for c[*] destination which can be constant or have an
offset of a1.x.
</doc>
<encode type="struct ir3_instruction *" case-prefix="">
<map name="OFFSET">extract_reg_uim(src->srcs[0])</map>
</encode>
</bitset>
<bitset name="#instruction-cat6" extends="#instruction">
<field pos="59" name="JP" type="bool" display="(jp)"/>
<field pos="60" name="SY" type="bool" display="(sy)"/>
@ -149,6 +176,41 @@ SOFTWARE.
</encode>
</bitset>
<bitset name="ldg.k" extends="#instruction-cat6-a3xx">
<doc>
LoaD Global Constants
</doc>
<gen min="600"/>
<display>
{SY}{JP}{NAME}.{TYPE} c[{DST}], g[{SRC1}{OFF}], {SIZE}
</display>
<pattern pos="0" >1</pattern>
<field low="1" high="13" name="OFF" type="offset"/>
<field low="14" high="21" name="SRC1" type="#cat6-src-const-or-gpr">
<param name="SRC1_CONST" as="SRC_CONST"/>
</field>
<pattern pos="22" >0</pattern>
<field low="23" high="26" name="SIZE" type="uint"/>
<pattern low="27" high="31">00xxx</pattern>
<field low="32" high="40" name="DST" type="#const-dst"/>
<pattern low="41" high="48">xxxxxxxx</pattern>
<pattern pos="52" >1</pattern>
<pattern low="53" high="53">0</pattern>
<pattern low="54" high="58">00000</pattern> <!-- OPC -->
<derived name="SRC1_CONST" expr="#false" type="bool"/>
<encode>
<map name="DST">src</map>
<map name="SRC1">src->srcs[1]</map>
<map name="OFF">extract_reg_uim(src->srcs[2])</map>
<map name="SIZE">extract_reg_uim(src->srcs[3])</map>
</encode>
</bitset>
<bitset name="#instruction-cat6-stg" extends="#instruction-cat6-a3xx">
<pattern pos="0" >x</pattern>
<field low="1" high="8" name="SRC3" type="#reg-gpr"/>
@ -392,32 +454,6 @@ SOFTWARE.
<pattern low="54" high="58">01011</pattern> <!-- OPC -->
</bitset>
<bitset name="#stc-dst-imm" extends="#stc-dst">
<display>
{OFFSET}
</display>
<field name="OFFSET" low="0" high="7" type="uint"/>
<pattern pos="8">0</pattern>
</bitset>
<bitset name="#stc-dst-a1" extends="#stc-dst">
<display>
a1.x{OFFSET}
</display>
<field name="OFFSET" low="0" high="7" type="uoffset"/>
<pattern pos="8">1</pattern>
</bitset>
<bitset name="#stc-dst" size="9">
<doc>
Encoding for stc destination which can be constant or have an
offset of a1.x.
</doc>
<encode type="struct ir3_instruction *" case-prefix="">
<map name="OFFSET">extract_reg_uim(src->srcs[0])</map>
</encode>
</bitset>
<bitset name="stc" extends="#instruction-cat6-a3xx">
<doc>
STore Const - used for shader prolog (between shps and shpe)
@ -450,7 +486,7 @@ SOFTWARE.
<pattern pos="23" >1</pattern>
<field low="24" high="26" name="SIZE" type="uint"/>
<pattern low="27" high="31">xxxxx</pattern>
<field low="32" high="40" name="DST" type="#stc-dst"/>
<field low="32" high="40" name="DST" type="#const-dst"/>
<pattern low="41" high="48">xxxxxxxx</pattern>
<pattern low="52" high="53">xx</pattern>
<pattern low="54" high="58">11100</pattern> <!-- OPC -->