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r300: don't flush VAP too often.
Flush the VAP the first time for each state atom we upload new VAP data
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parent
199867bd45
commit
bc5f94c1e1
4 changed files with 21 additions and 7 deletions
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@ -97,14 +97,20 @@ void emit_vpu(GLcontext *ctx, struct radeon_state_atom * atom)
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addr = (cmd.vpu.adrhi << 8) | cmd.vpu.adrlo;
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ndw = cmd.vpu.count * 4;
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if (ndw) {
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BEGIN_BATCH_NO_AUTOSTATE(15 + ndw);
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/* flush processing vertices */
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OUT_BATCH_REGVAL(R300_SC_SCREENDOOR, 0);
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OUT_BATCH_REGVAL(R300_RB3D_DSTCACHE_CTLSTAT, R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D);
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OUT_BATCH_REGVAL(RADEON_WAIT_UNTIL, RADEON_WAIT_3D_IDLECLEAN);
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OUT_BATCH_REGVAL(R300_SC_SCREENDOOR, 0xffffff);
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OUT_BATCH_REGVAL(R300_VAP_PVS_STATE_FLUSH_REG, 1);
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if (r300->vap_flush_needed) {
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BEGIN_BATCH_NO_AUTOSTATE(15 + ndw);
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/* flush processing vertices */
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OUT_BATCH_REGVAL(R300_SC_SCREENDOOR, 0);
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OUT_BATCH_REGVAL(R300_RB3D_DSTCACHE_CTLSTAT, R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D);
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OUT_BATCH_REGVAL(RADEON_WAIT_UNTIL, RADEON_WAIT_3D_IDLECLEAN);
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OUT_BATCH_REGVAL(R300_SC_SCREENDOOR, 0xffffff);
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OUT_BATCH_REGVAL(R300_VAP_PVS_STATE_FLUSH_REG, 0);
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r300->vap_flush_needed = GL_FALSE;
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} else {
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BEGIN_BATCH_NO_AUTOSTATE(5 + ndw);
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}
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OUT_BATCH_REGVAL(R300_VAP_PVS_UPLOAD_ADDRESS, addr);
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OUT_BATCH(CP_PACKET0(R300_VAP_PVS_UPLOAD_DATA, ndw-1) | RADEON_ONE_REG_WR);
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for (i = 0; i < ndw; i++) {
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@ -235,7 +235,11 @@ static void r300_vtbl_emit_cs_header(struct radeon_cs *cs, radeonContextPtr rmes
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static void r300_vtbl_pre_emit_atoms(radeonContextPtr radeon)
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{
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r300ContextPtr r300 = (r300ContextPtr)radeon;
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BATCH_LOCALS(radeon);
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r300->vap_flush_needed = GL_TRUE;
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cp_wait(radeon, R300_WAIT_3D | R300_WAIT_3D_CLEAN);
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BEGIN_BATCH_NO_AUTOSTATE(2);
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OUT_BATCH_REGVAL(R300_TX_INVALTAGS, R300_TX_FLUSH);
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@ -683,7 +683,9 @@ struct r300_context {
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GLboolean disable_lowimpact_fallback;
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DECLARE_RENDERINPUTS(tnl_index_bitset); /* index of bits for last tnl_install_attrs */
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struct r300_swtcl_info swtcl;
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GLboolean vap_flush_needed;
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};
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struct r300_buffer_object {
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@ -528,6 +528,8 @@ static void r300EmitClearState(GLcontext * ctx)
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PVS_SRC_SELECT_FORCE_0,
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PVS_SRC_REG_INPUT, VSF_FLAG_NONE);
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vpu.cmd[8] = 0x0;
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r300->vap_flush_needed = GL_TRUE;
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emit_vpu(ctx, &vpu);
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}
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}
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