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Lots of updates for new gl_renderbuffer ClassID and _ActualFormat fields.

Browse source 
Removed hw_stencil field from context.  Now determine hw stencil from looking
at the stencil renderbuffer.
Enabled the GL_EXT_packed_depth_stencil extension.  May not be permanent but
for now it allows hw stencil to work with the fbotexture.c demo (w/ -ds flag).
Using separate renderbuffers for GL_DEPTH_ATTACHMENT_EXT and
GL_STENCIL_ATTACHMENT_EXT works, but is currently a software fallback.
This commit is contained in:
Brian Paul 2006-03-21 23:58:03 +00:00
parent 3a3db0e9ec
commit bc400c3f30
8 changed files with 119 additions and 76 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

40
src/mesa/drivers/dri/i915/i830_state.c
View file

@ -36,6 +36,7 @@
#include "intel_screen.h"
#include "intel_batchbuffer.h"
#include "intel_fbo.h"
#include "i830_context.h"
#include "i830_reg.h"
@ -806,20 +807,28 @@ static void i830Enable(GLcontext *ctx, GLenum cap, GLboolean state)
break;
case GL_STENCIL_TEST:
if (i830->intel.hw_stencil) {
I830_STATECHANGE(i830, I830_UPLOAD_CTX);
{
GLboolean hw_stencil = GL_FALSE;
if (ctx->DrawBuffer) {
struct intel_renderbuffer *irbStencil
= intel_get_renderbuffer(ctx->DrawBuffer, BUFFER_STENCIL);
hw_stencil = (irbStencil && irbStencil->region);
}
if (hw_stencil) {
I830_STATECHANGE(i830, I830_UPLOAD_CTX);
if (state) {
i830->state.Ctx[I830_CTXREG_ENABLES_1] |= ENABLE_STENCIL_TEST;
i830->state.Ctx[I830_CTXREG_ENABLES_2] |= ENABLE_STENCIL_WRITE;
} else {
i830->state.Ctx[I830_CTXREG_ENABLES_1] &= ~ENABLE_STENCIL_TEST;
i830->state.Ctx[I830_CTXREG_ENABLES_2] &= ~ENABLE_STENCIL_WRITE;
i830->state.Ctx[I830_CTXREG_ENABLES_1] |= DISABLE_STENCIL_TEST;
i830->state.Ctx[I830_CTXREG_ENABLES_2] |= DISABLE_STENCIL_WRITE;
}
} else {
FALLBACK( &i830->intel, I830_FALLBACK_STENCIL, state );
if (state) {
i830->state.Ctx[I830_CTXREG_ENABLES_1] |= ENABLE_STENCIL_TEST;
i830->state.Ctx[I830_CTXREG_ENABLES_2] |= ENABLE_STENCIL_WRITE;
} else {
i830->state.Ctx[I830_CTXREG_ENABLES_1] &= ~ENABLE_STENCIL_TEST;
i830->state.Ctx[I830_CTXREG_ENABLES_2] &= ~ENABLE_STENCIL_WRITE;
i830->state.Ctx[I830_CTXREG_ENABLES_1] |= DISABLE_STENCIL_TEST;
i830->state.Ctx[I830_CTXREG_ENABLES_2] |= DISABLE_STENCIL_WRITE;
}
} else {
FALLBACK( &i830->intel, I830_FALLBACK_STENCIL, state );
}
}
break;
@ -902,6 +911,7 @@ static void i830_init_packets( struct i830_context *i830 )
DISABLE_COLOR_BLEND |
DISABLE_DEPTH_TEST);
#if 000 /* XXX all the stencil enable state is set in i830Enable(), right? */
if (i830->intel.hw_stencil) {
i830->state.Ctx[I830_CTXREG_ENABLES_2] = (_3DSTATE_ENABLES_2_CMD |
ENABLE_STENCIL_WRITE |
@ -911,7 +921,9 @@ static void i830_init_packets( struct i830_context *i830 )
/* set no color comps disabled */
ENABLE_COLOR_WRITE |
ENABLE_DEPTH_WRITE);
} else {
} else
#endif
{
i830->state.Ctx[I830_CTXREG_ENABLES_2] = (_3DSTATE_ENABLES_2_CMD |
DISABLE_STENCIL_WRITE |
ENABLE_TEX_CACHE |

30
src/mesa/drivers/dri/i915/i915_state.c
View file

@ -36,6 +36,7 @@
#include "texmem.h"
#include "intel_fbo.h"
#include "intel_screen.h"
#include "intel_batchbuffer.h"
@ -672,6 +673,7 @@ static void i915Hint(GLcontext *ctx, GLenum target, GLenum state)
static void i915Enable(GLcontext *ctx, GLenum cap, GLboolean state)
{
struct i915_context *i915 = I915_CONTEXT(ctx);
int hw_stencil;
switch(cap) {
case GL_TEXTURE_2D:
@ -750,16 +752,24 @@ static void i915Enable(GLcontext *ctx, GLenum cap, GLboolean state)
break;
case GL_STENCIL_TEST:
if (i915->intel.hw_stencil) {
I915_STATECHANGE(i915, I915_UPLOAD_CTX);
if (state)
i915->state.Ctx[I915_CTXREG_LIS5] |= (S5_STENCIL_TEST_ENABLE |
S5_STENCIL_WRITE_ENABLE);
else
i915->state.Ctx[I915_CTXREG_LIS5] &= ~(S5_STENCIL_TEST_ENABLE |
S5_STENCIL_WRITE_ENABLE);
} else {
FALLBACK( &i915->intel, I915_FALLBACK_STENCIL, state );
{
GLboolean hw_stencil = GL_FALSE;
if (ctx->DrawBuffer) {
struct intel_renderbuffer *irbStencil
= intel_get_renderbuffer(ctx->DrawBuffer, BUFFER_STENCIL);
hw_stencil = (irbStencil && irbStencil->region);
}
if (hw_stencil) {
I915_STATECHANGE(i915, I915_UPLOAD_CTX);
if (state)
i915->state.Ctx[I915_CTXREG_LIS5] |= (S5_STENCIL_TEST_ENABLE |
S5_STENCIL_WRITE_ENABLE);
else
i915->state.Ctx[I915_CTXREG_LIS5] &= ~(S5_STENCIL_TEST_ENABLE |
S5_STENCIL_WRITE_ENABLE);
} else {
FALLBACK( &i915->intel, I915_FALLBACK_STENCIL, state );
}
}
break;

29
src/mesa/drivers/dri/i915/intel_buffers.c
View file

@ -394,14 +394,19 @@ static void intelClear(GLcontext *ctx,
}
/* HW stencil */
if (intel->hw_stencil && (mask & BUFFER_BIT_STENCIL)) {
if ((ctx->Stencil.WriteMask[0] & 0xff) != 0xff) {
/* not clearing all stencil bits, so use triangle clearing */
tri_mask |= BUFFER_BIT_STENCIL;
}
else {
/* clearing all stencil bits, use blitting */
blit_mask |= BUFFER_BIT_STENCIL;
if (mask & BUFFER_BIT_STENCIL) {
const struct intel_region *stencilRegion
= intel_get_rb_region(ctx->DrawBuffer, BUFFER_STENCIL);
if (stencilRegion) {
/* have hw stencil */
if ((ctx->Stencil.WriteMask[0] & 0xff) != 0xff) {
/* not clearing all stencil bits, so use triangle clearing */
tri_mask |= BUFFER_BIT_STENCIL;
}
else {
/* clearing all stencil bits, use blitting */
blit_mask |= BUFFER_BIT_STENCIL;
}
}
}
@ -544,7 +549,7 @@ intel_draw_buffer(GLcontext *ctx, struct gl_framebuffer *fb)
if (fb->_NumColorDrawBuffers[0] != 1
#if 0
/* XXX FBO temporary - always use software rendering */
|| fb->Name != 0
|| 1
#endif
) {
/* writing to 0 or 2 or 4 color buffers */
@ -636,15 +641,19 @@ intel_draw_buffer(GLcontext *ctx, struct gl_framebuffer *fb)
irbStencil = intel_get_renderbuffer(fb, BUFFER_STENCIL);
if (irbStencil) {
if (irbStencil == irbDepth && irbStencil->region) {
ASSERT(irbStencil->Base._ActualFormat == GL_DEPTH24_STENCIL8_EXT);
FALLBACK(intel, INTEL_FALLBACK_STENCIL_BUFFER, GL_FALSE);
/* need to re-compute stencil hw state */
ctx->Driver.Enable(ctx, GL_STENCIL_TEST, ctx->Stencil.Enabled);
}
else {
FALLBACK(intel, INTEL_FALLBACK_STENCIL_BUFFER, GL_TRUE);
ASSERT(irbStencil->Base.InternalFormat == GL_DEPTH24_STENCIL8_EXT);
}
}
else {
FALLBACK(intel, INTEL_FALLBACK_STENCIL_BUFFER, GL_FALSE);
/* need to re-compute stencil hw state */
ctx->Driver.Enable(ctx, GL_STENCIL_TEST, ctx->Stencil.Enabled);
}
intel->vtbl.set_draw_region( intel, colorRegion, depthRegion );

4
src/mesa/drivers/dri/i915/intel_context.c
View file

@ -170,6 +170,9 @@ const struct dri_extension card_extensions[] =
{ "GL_EXT_fog_coord", GL_EXT_fog_coord_functions },
{ "GL_EXT_framebuffer_object", GL_EXT_framebuffer_object_functions },
{ "GL_EXT_multi_draw_arrays", GL_EXT_multi_draw_arrays_functions },
#if 1 /* XXX FBO temporary? */
{ "GL_EXT_packed_depth_stencil", NULL },
#endif
{ "GL_EXT_secondary_color", GL_EXT_secondary_color_functions },
{ "GL_EXT_stencil_wrap", NULL },
{ "GL_EXT_texture_edge_clamp", NULL },
@ -346,7 +349,6 @@ GLboolean intelInitContext( struct intel_context *intel,
intel->driFd = sPriv->fd;
intel->driHwLock = (drmLock *) &sPriv->pSAREA->lock;
intel->hw_stencil = mesaVis->stencilBits && mesaVis->depthBits == 24;
intel->hw_stipple = 1;
/* XXX FBO: this doesn't seem to be used anywhere */

1
src/mesa/drivers/dri/i915/intel_context.h
View file

@ -198,7 +198,6 @@ struct intel_context
GLfloat polygon_offset_scale; /* dependent on depth_scale, bpp */
GLboolean hw_stencil;
GLboolean hw_stipple;
/* AGP memory buffer manager:

76
src/mesa/drivers/dri/i915/intel_fbo.c
View file

@ -43,16 +43,24 @@
#include "intel_span.h"
#define MAGIC 0x12345678
#define INTEL_RB_CLASS 0x12345678
/* XXX FBO: move this to intel_context.h (inlined) */
/**
* Return a gl_renderbuffer ptr casted to intel_renderbuffer.
* NULL will be returned if the rb isn't really an intel_renderbuffer.
* This is determiend by checking the ClassID.
*/
struct intel_renderbuffer *intel_renderbuffer( struct gl_renderbuffer *rb )
{
struct intel_renderbuffer *irb = (struct intel_renderbuffer *) rb;
if (irb) {
assert(irb->Magic == 0x12345678);
if (irb && irb->Base.ClassID == INTEL_RB_CLASS) {
/*_mesa_warning(NULL, "Returning non-intel Rb\n");*/
return irb;
}
return irb;
else
return NULL;
}
@ -161,7 +169,7 @@ intel_alloc_renderbuffer_storage(GLcontext *ctx, struct gl_renderbuffer *rb,
case GL_R3_G3_B2:
case GL_RGB4:
case GL_RGB5:
rb->InternalFormat = GL_RGB5;
rb->_ActualFormat = GL_RGB5;
rb->DataType = GL_UNSIGNED_BYTE;
rb->RedBits = 5;
rb->GreenBits = 6;
@ -181,7 +189,7 @@ intel_alloc_renderbuffer_storage(GLcontext *ctx, struct gl_renderbuffer *rb,
case GL_RGB10_A2:
case GL_RGBA12:
case GL_RGBA16:
rb->InternalFormat = GL_RGBA8;
rb->_ActualFormat = GL_RGBA8;
rb->DataType = GL_UNSIGNED_BYTE;
rb->RedBits = 8;
rb->GreenBits = 8;
@ -194,7 +202,7 @@ intel_alloc_renderbuffer_storage(GLcontext *ctx, struct gl_renderbuffer *rb,
case GL_STENCIL_INDEX4_EXT:
case GL_STENCIL_INDEX8_EXT:
case GL_STENCIL_INDEX16_EXT:
rb->InternalFormat = GL_STENCIL_INDEX8_EXT;
rb->_ActualFormat = GL_STENCIL_INDEX8_EXT;
rb->DataType = GL_UNSIGNED_BYTE;
rb->StencilBits = 8;
cpp = 1;
@ -202,7 +210,7 @@ intel_alloc_renderbuffer_storage(GLcontext *ctx, struct gl_renderbuffer *rb,
/* XXX software buffer? */
break;
case GL_DEPTH_COMPONENT16:
rb->InternalFormat = GL_DEPTH_COMPONENT16;
rb->_ActualFormat = GL_DEPTH_COMPONENT16;
rb->DataType = GL_UNSIGNED_SHORT;
rb->DepthBits = 16;
cpp = 2;
@ -210,14 +218,14 @@ intel_alloc_renderbuffer_storage(GLcontext *ctx, struct gl_renderbuffer *rb,
case GL_DEPTH_COMPONENT:
case GL_DEPTH_COMPONENT24:
case GL_DEPTH_COMPONENT32:
rb->InternalFormat = GL_DEPTH24_STENCIL8_EXT;
rb->_ActualFormat = GL_DEPTH24_STENCIL8_EXT;
rb->DataType = GL_UNSIGNED_INT_24_8_EXT;
rb->DepthBits = 24;
cpp = 4;
break;
case GL_DEPTH_STENCIL_EXT:
case GL_DEPTH24_STENCIL8_EXT:
rb->InternalFormat = GL_DEPTH24_STENCIL8_EXT;
rb->_ActualFormat = GL_DEPTH24_STENCIL8_EXT;
rb->DataType = GL_UNSIGNED_INT_24_8_EXT;
rb->DepthBits = 24;
rb->StencilBits = 8;
@ -279,7 +287,7 @@ intel_alloc_window_storage(GLcontext *ctx, struct gl_renderbuffer *rb,
ASSERT(rb->Name == 0);
rb->Width = width;
rb->Height = height;
rb->InternalFormat = internalFormat;
rb->_ActualFormat = internalFormat;
return GL_TRUE;
}
@ -316,9 +324,8 @@ intel_create_renderbuffer(GLenum intFormat, GLsizei width, GLsizei height,
return NULL;
}
irb->Magic = MAGIC; /* XXX FBO temporary */
_mesa_init_renderbuffer(&irb->Base, name);
irb->Base.ClassID = INTEL_RB_CLASS;
switch (intFormat) {
case GL_RGB5:
@ -368,7 +375,7 @@ intel_create_renderbuffer(GLenum intFormat, GLsizei width, GLsizei height,
return NULL;
}
irb->Base.InternalFormat = intFormat;
irb->Base._ActualFormat = intFormat;
/* intel-specific methods */
irb->Base.Delete = intel_delete_renderbuffer;
@ -409,9 +416,8 @@ intel_new_renderbuffer(GLcontext *ctx, GLuint name)
return NULL;
}
irb->Magic = MAGIC;
_mesa_init_renderbuffer(&irb->Base, name);
irb->Base.ClassID = INTEL_RB_CLASS;
/* intel-specific methods */
irb->Base.Delete = intel_delete_renderbuffer;
@ -481,28 +487,30 @@ intel_wrap_texture(GLcontext *ctx, struct gl_texture_image *texImage)
}
_mesa_init_renderbuffer(&irb->Base, name);
irb->Magic = MAGIC; /* XXX FBO temporary */
irb->Base.ClassID = INTEL_RB_CLASS;
if (texImage->TexFormat == &_mesa_texformat_argb8888) {
irb->Base.InternalFormat = GL_RGBA8;
irb->Base._ActualFormat = GL_RGBA8;
irb->Base._BaseFormat = GL_RGBA;
_mesa_debug(ctx, "Render to RGBA8 texture OK\n");
}
else if (texImage->TexFormat == &_mesa_texformat_rgb565) {
irb->Base.InternalFormat = GL_RGB5;
irb->Base._ActualFormat = GL_RGB5;
irb->Base._BaseFormat = GL_RGB;
_mesa_debug(ctx, "Render to RGB5 texture OK\n");
}
else if (texImage->TexFormat == &_mesa_texformat_depth_component16) {
irb->Base.InternalFormat = GL_DEPTH_COMPONENT16;
irb->Base._ActualFormat = GL_DEPTH_COMPONENT16;
irb->Base._BaseFormat = GL_DEPTH_COMPONENT;
_mesa_debug(ctx, "Render to DEPTH16 texture OK\n");
}
else {
_mesa_debug(ctx, "Render to texture BAD FORMAT\n");
/* XXX will need to use software rendering! */
_mesa_free(irb);
return NULL;
}
irb->Base.InternalFormat = irb->Base._ActualFormat;
irb->Base.Width = texImage->Width;
irb->Base.Height = texImage->Height;
irb->Base.DataType = GL_UNSIGNED_BYTE; /* FBO XXX fix */
@ -545,21 +553,25 @@ intel_renderbuffer_texture(GLcontext *ctx,
if (!irb) {
irb = intel_wrap_texture(ctx, newImage);
if (!irb) {
_mesa_error(ctx, GL_OUT_OF_MEMORY, "render to texture");
return;
}
att->Renderbuffer = &irb->Base;
}
irb->Base.RefCount++;
if (irb) {
/* hardware rendering to texture */
irb->Base.RefCount++;
/* hook into the region */
/* XXX mipmap level / cube face */
intel_image = intel_texture_image(newImage);
intel_region_reference(&irb->region, intel_image->mt->region);
/* hook into the region */
/* XXX mipmap level / cube face */
intel_image = intel_texture_image(newImage);
intel_region_reference(&irb->region, intel_image->mt->region);
att->Renderbuffer = &irb->Base;
intel_draw_buffer(ctx, fb);
intel_draw_buffer(ctx, fb);
}
else {
/* fallback to software rendering */
_mesa_problem(ctx, "Render to texture - unsupported hw format");
}
}

1
src/mesa/drivers/dri/i915/intel_fbo.h
View file

@ -41,7 +41,6 @@ struct intel_renderbuffer {
struct intel_region *region;
void *pfMap; /* possibly paged flipped map pointer */
GLuint pfPitch; /* possibly paged flipped pitch */
GLuint Magic; /* for debug/sanity */
GLboolean RenderToTexture; /* RTT? */
};

14
src/mesa/drivers/dri/i915/intel_span.c
View file

@ -342,25 +342,25 @@ void intelInitSpanFuncs( GLcontext *ctx )
void
intel_set_span_functions(struct gl_renderbuffer *rb)
{
if (rb->InternalFormat == GL_RGB5) {
if (rb->_ActualFormat == GL_RGB5) {
/* 565 RGB */
intelInitPointers_RGB565(rb);
}
else if (rb->InternalFormat == GL_RGBA8) {
else if (rb->_ActualFormat == GL_RGBA8) {
/* 8888 RGBA */
intelInitPointers_ARGB8888(rb);
}
else if (rb->InternalFormat == GL_DEPTH_COMPONENT16) {
else if (rb->_ActualFormat == GL_DEPTH_COMPONENT16) {
intelInitDepthPointers_z16(rb);
}
else if (rb->InternalFormat == GL_DEPTH_COMPONENT24 || /* XXX FBO remove */
rb->InternalFormat == GL_DEPTH24_STENCIL8_EXT) {
else if (rb->_ActualFormat == GL_DEPTH_COMPONENT24 || /* XXX FBO remove */
rb->_ActualFormat == GL_DEPTH24_STENCIL8_EXT) {
intelInitDepthPointers_z24_s8(rb);
}
else if (rb->InternalFormat == GL_STENCIL_INDEX8_EXT) { /* XXX FBO remove */
else if (rb->_ActualFormat == GL_STENCIL_INDEX8_EXT) { /* XXX FBO remove */
intelInitStencilPointers_z24_s8(rb);
}
else {
_mesa_problem(NULL, "Unexpected InternalFormat in intelSetSpanFunctions");
_mesa_problem(NULL, "Unexpected _ActualFormat in intelSetSpanFunctions");
}
}