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r600g: atomize alphatest state

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This commit is contained in:
Marek Olšák 2012-07-18 03:45:25 +02:00
parent 5130196c0b
commit bc2f5fc01e
6 changed files with 52 additions and 46 deletions
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4
src/gallium/drivers/r600/evergreen_hw_context.c
View file

@ -73,14 +73,12 @@ static const struct r600_reg evergreen_context_reg_list[] = {
{R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0, 0},
{R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, 0, 0},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_028410_SX_ALPHA_TEST_CONTROL, 0, 0},
{R_028414_CB_BLEND_RED, 0, 0},
{R_028418_CB_BLEND_GREEN, 0, 0},
{R_02841C_CB_BLEND_BLUE, 0, 0},
{R_028420_CB_BLEND_ALPHA, 0, 0},
{R_028430_DB_STENCILREFMASK, 0, 0},
{R_028434_DB_STENCILREFMASK_BF, 0, 0},
{R_028438_SX_ALPHA_REF, 0, 0},
{R_02843C_PA_CL_VPORT_XSCALE_0, 0, 0},
{R_028440_PA_CL_VPORT_XOFFSET_0, 0, 0},
{R_028444_PA_CL_VPORT_YSCALE_0, 0, 0},
@ -330,14 +328,12 @@ static const struct r600_reg cayman_context_reg_list[] = {
{R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0, 0},
{R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, 0, 0},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_028410_SX_ALPHA_TEST_CONTROL, 0, 0},
{R_028414_CB_BLEND_RED, 0, 0},
{R_028418_CB_BLEND_GREEN, 0, 0},
{R_02841C_CB_BLEND_BLUE, 0, 0},
{R_028420_CB_BLEND_ALPHA, 0, 0},
{R_028430_DB_STENCILREFMASK, 0, 0},
{R_028434_DB_STENCILREFMASK_BF, 0, 0},
{R_028438_SX_ALPHA_REF, 0, 0},
{R_02843C_PA_CL_VPORT_XSCALE_0, 0, 0},
{R_028440_PA_CL_VPORT_XOFFSET_0, 0, 0},
{R_028444_PA_CL_VPORT_YSCALE_0, 0, 0},

16
src/gallium/drivers/r600/evergreen_state.c
View file

@ -1263,7 +1263,7 @@ void evergreen_cb(struct r600_context *rctx, struct r600_pipe_state *rstate,
unsigned tile_type, macro_aspect, tile_split, bankh, bankw, nbanks;
const struct util_format_description *desc;
int i;
unsigned blend_clamp = 0, blend_bypass = 0;
bool blend_clamp = 0, blend_bypass = 0, alphatest_bypass;
surf = (struct r600_surface *)state->cbufs[cb];
rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
@ -1397,10 +1397,11 @@ void evergreen_cb(struct r600_context *rctx, struct r600_pipe_state *rstate,
blend_bypass = 1;
}
if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT)
rctx->sx_alpha_test_control |= S_028410_ALPHA_TEST_BYPASS(1);
else
rctx->sx_alpha_test_control &= C_028410_ALPHA_TEST_BYPASS;
alphatest_bypass = ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT;
if (rctx->alphatest_state.bypass != alphatest_bypass) {
rctx->alphatest_state.bypass = alphatest_bypass;
r600_atom_dirty(rctx, &rctx->alphatest_state.atom);
}
color_info |= S_028C70_FORMAT(format) |
S_028C70_COMP_SWAP(swap) |
@ -1433,7 +1434,6 @@ void evergreen_cb(struct r600_context *rctx, struct r600_pipe_state *rstate,
} else {
rctx->export_16bpc = false;
}
rctx->alpha_ref_dirty = true;
/* for possible dual-src MRT */
if (cb == 0 && rctx->framebuffer.nr_cbufs == 1 && !rtex->is_rat) {
@ -1681,6 +1681,10 @@ static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
rctx->cb_misc_state.nr_cbufs = state->nr_cbufs;
r600_atom_dirty(rctx, &rctx->cb_misc_state.atom);
}
if (rctx->alphatest_state.export_16bpc != rctx->export_16bpc) {
rctx->alphatest_state.export_16bpc = rctx->export_16bpc;
r600_atom_dirty(rctx, &rctx->alphatest_state.atom);
}
}
static void evergreen_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom *atom)

3
src/gallium/drivers/r600/r600_hw_context.c
View file

@ -330,7 +330,6 @@ static const struct r600_reg r600_context_reg_list[] = {
{R_028124_CB_CLEAR_GREEN, 0, 0},
{R_028128_CB_CLEAR_BLUE, 0, 0},
{R_02812C_CB_CLEAR_ALPHA, 0, 0},
{R_028410_SX_ALPHA_TEST_CONTROL, 0, 0},
{R_028414_CB_BLEND_RED, 0, 0},
{R_028418_CB_BLEND_GREEN, 0, 0},
{R_02841C_CB_BLEND_BLUE, 0, 0},
@ -340,7 +339,6 @@ static const struct r600_reg r600_context_reg_list[] = {
{R_02842C_CB_FOG_BLUE, 0, 0},
{R_028430_DB_STENCILREFMASK, 0, 0},
{R_028434_DB_STENCILREFMASK_BF, 0, 0},
{R_028438_SX_ALPHA_REF, 0, 0},
{R_028780_CB_BLEND0_CONTROL, REG_FLAG_NOT_R600, 0},
{R_028784_CB_BLEND1_CONTROL, REG_FLAG_NOT_R600, 0},
{R_028788_CB_BLEND2_CONTROL, REG_FLAG_NOT_R600, 0},
@ -1090,6 +1088,7 @@ void r600_context_flush(struct r600_context *ctx, unsigned flags)
r600_flush_framebuffer(ctx, false);
/* Re-emit states. */
r600_atom_dirty(ctx, &ctx->alphatest_state.atom);
r600_atom_dirty(ctx, &ctx->cb_misc_state.atom);
r600_atom_dirty(ctx, &ctx->db_misc_state.atom);

12
src/gallium/drivers/r600/r600_pipe.h
View file

@ -92,6 +92,14 @@ struct r600_cb_misc_state {
bool dual_src_blend;
};
struct r600_alphatest_state {
struct r600_atom atom;
unsigned sx_alpha_test_control; /* this comes from dsa state */
unsigned sx_alpha_ref; /* this comes from dsa state */
bool bypass;
bool export_16bpc; /* from set_framebuffer_state */
};
enum r600_pipe_state_id {
R600_PIPE_STATE_BLEND = 0,
R600_PIPE_STATE_BLEND_COLOR,
@ -307,7 +315,6 @@ struct r600_context {
struct r600_vertex_element *vertex_elements;
struct pipe_framebuffer_state framebuffer;
unsigned compute_cb_target_mask;
unsigned sx_alpha_test_control;
unsigned db_shader_control;
unsigned pa_sc_line_stipple;
unsigned pa_cl_clip_cntl;
@ -331,8 +338,6 @@ struct r600_context {
unsigned sprite_coord_enable;
boolean flatshade;
boolean export_16bpc;
unsigned alpha_ref;
boolean alpha_ref_dirty;
unsigned nr_cbufs;
struct u_upload_mgr *uploader;
@ -348,6 +353,7 @@ struct r600_context {
struct r600_command_buffer start_compute_cs_cmd;
struct r600_surface_sync_cmd surface_sync_cmd;
struct r600_atom r6xx_flush_and_inv_cmd;
struct r600_alphatest_state alphatest_state;
struct r600_cb_misc_state cb_misc_state;
struct r600_db_misc_state db_misc_state;
/** Vertex buffers for fetch shaders */

11
src/gallium/drivers/r600/r600_state.c
View file

@ -1335,7 +1335,7 @@ static void r600_cb(struct r600_context *rctx, struct r600_pipe_state *rstate,
unsigned offset;
const struct util_format_description *desc;
int i;
unsigned blend_bypass = 0, blend_clamp = 1;
bool blend_bypass = 0, blend_clamp = 1, alphatest_bypass;
surf = (struct r600_surface *)state->cbufs[cb];
rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
@ -1426,10 +1426,11 @@ static void r600_cb(struct r600_context *rctx, struct r600_pipe_state *rstate,
blend_bypass = 1;
}
if (ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT)
rctx->sx_alpha_test_control |= S_028410_ALPHA_TEST_BYPASS(1);
else
rctx->sx_alpha_test_control &= C_028410_ALPHA_TEST_BYPASS;
alphatest_bypass = ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT;
if (rctx->alphatest_state.bypass != alphatest_bypass) {
rctx->alphatest_state.bypass = alphatest_bypass;
r600_atom_dirty(rctx, &rctx->alphatest_state.atom);
}
color_info |= S_0280A0_FORMAT(format) |
S_0280A0_COMP_SWAP(swap) |

52
src/gallium/drivers/r600/r600_state_common.c
View file

@ -86,10 +86,28 @@ void r600_init_atom(struct r600_atom *atom,
atom->flags = flags;
}
static void r600_emit_alphatest_state(struct r600_context *rctx, struct r600_atom *atom)
{
struct radeon_winsys_cs *cs = rctx->cs;
struct r600_alphatest_state *a = (struct r600_alphatest_state*)atom;
unsigned alpha_ref = a->sx_alpha_ref;
if (rctx->chip_class >= EVERGREEN && a->export_16bpc) {
alpha_ref &= ~0x1FFF;
}
r600_write_context_reg(cs, R_028410_SX_ALPHA_TEST_CONTROL,
a->sx_alpha_test_control |
S_028410_ALPHA_TEST_BYPASS(a->bypass));
r600_write_context_reg(cs, R_028438_SX_ALPHA_REF, alpha_ref);
}
void r600_init_common_atoms(struct r600_context *rctx)
{
r600_init_atom(&rctx->surface_sync_cmd.atom, r600_emit_surface_sync, 5, EMIT_EARLY);
r600_init_atom(&rctx->r6xx_flush_and_inv_cmd, r600_emit_r6xx_flush_and_inv, 2, EMIT_EARLY);
r600_init_atom(&rctx->alphatest_state.atom, r600_emit_alphatest_state, 3, 0);
r600_atom_dirty(rctx, &rctx->alphatest_state.atom);
}
unsigned r600_get_cb_flush_flags(struct r600_context *rctx)
@ -258,10 +276,6 @@ void r600_bind_dsa_state(struct pipe_context *ctx, void *state)
return;
rstate = &dsa->rstate;
rctx->states[rstate->id] = rstate;
rctx->sx_alpha_test_control &= ~0xff;
rctx->sx_alpha_test_control |= dsa->sx_alpha_test_control;
rctx->alpha_ref = dsa->alpha_ref;
rctx->alpha_ref_dirty = true;
r600_context_pipe_state_set(rctx, rstate);
ref.ref_value[0] = rctx->stencil_ref.ref_value[0];
@ -272,6 +286,14 @@ void r600_bind_dsa_state(struct pipe_context *ctx, void *state)
ref.writemask[1] = dsa->writemask[1];
r600_set_stencil_ref(ctx, &ref);
/* Update alphatest state. */
if (rctx->alphatest_state.sx_alpha_test_control != dsa->sx_alpha_test_control ||
rctx->alphatest_state.sx_alpha_ref != dsa->alpha_ref) {
rctx->alphatest_state.sx_alpha_test_control = dsa->sx_alpha_test_control;
rctx->alphatest_state.sx_alpha_ref = dsa->alpha_ref;
r600_atom_dirty(rctx, &rctx->alphatest_state.atom);
}
}
void r600_set_max_scissor(struct r600_context *rctx)
@ -758,22 +780,6 @@ void r600_delete_vs_shader(struct pipe_context *ctx, void *state)
r600_delete_shader_selector(ctx, sel);
}
static void r600_update_alpha_ref(struct r600_context *rctx)
{
unsigned alpha_ref;
struct r600_pipe_state rstate;
alpha_ref = rctx->alpha_ref;
rstate.nregs = 0;
if (rctx->export_16bpc && rctx->chip_class >= EVERGREEN) {
alpha_ref &= ~0x1FFF;
}
r600_pipe_state_add_reg(&rstate, R_028438_SX_ALPHA_REF, alpha_ref);
r600_context_pipe_state_set(rctx, &rstate);
rctx->alpha_ref_dirty = false;
}
void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state)
{
if (state->dirty_mask) {
@ -935,10 +941,6 @@ static void r600_update_derived_state(struct r600_context *rctx)
r600_shader_select(ctx, rctx->ps_shader, &ps_dirty);
if (rctx->alpha_ref_dirty) {
r600_update_alpha_ref(rctx);
}
if (rctx->ps_shader && ((rctx->sprite_coord_enable &&
(rctx->ps_shader->current->sprite_coord_enable != rctx->sprite_coord_enable)) ||
(rctx->rasterizer && rctx->rasterizer->flatshade != rctx->ps_shader->current->flatshade))) {
@ -1038,7 +1040,6 @@ void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo)
r600_pipe_state_add_reg(&rctx->vgt, R_028A6C_VGT_GS_OUT_PRIM_TYPE, 0);
r600_pipe_state_add_reg(&rctx->vgt, R_028408_VGT_INDX_OFFSET, info.index_bias);
r600_pipe_state_add_reg(&rctx->vgt, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, info.restart_index);
r600_pipe_state_add_reg(&rctx->vgt, R_028410_SX_ALPHA_TEST_CONTROL, 0);
r600_pipe_state_add_reg(&rctx->vgt, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, info.primitive_restart);
r600_pipe_state_add_reg(&rctx->vgt, R_03CFF4_SQ_VTX_START_INST_LOC, info.start_instance);
r600_pipe_state_add_reg(&rctx->vgt, R_028A0C_PA_SC_LINE_STIPPLE, 0);
@ -1051,7 +1052,6 @@ void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo)
r600_pipe_state_mod_reg(&rctx->vgt, r600_conv_prim_to_gs_out(info.mode));
r600_pipe_state_mod_reg(&rctx->vgt, info.index_bias);
r600_pipe_state_mod_reg(&rctx->vgt, info.restart_index);
r600_pipe_state_mod_reg(&rctx->vgt, rctx->sx_alpha_test_control);
r600_pipe_state_mod_reg(&rctx->vgt, info.primitive_restart);
r600_pipe_state_mod_reg(&rctx->vgt, info.start_instance);