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panfrost/midgard: Add "op commutes?" property
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
This commit is contained in:
Alyssa Rosenzweig
parent
1f345bc7d6
commit
bb1aff3007
2 changed files with 36 additions and 49 deletions
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@ -68,6 +68,9 @@
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#define QUIRK_FLIPPED_R24 (1 << 2)
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/* Is the op commutative? */
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#define OP_COMMUTES (1 << 3)
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/* Vector-independant shorthands for the above; these numbers are arbitrary and
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* not from the ISA. Convert to the above with unit_enum_to_midgard */
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@ -151,14 +154,14 @@ static struct {
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const char *name;
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unsigned props;
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} alu_opcode_props[256] = {
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[midgard_alu_op_fadd] = {"fadd", UNITS_ADD},
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[midgard_alu_op_fmul] = {"fmul", UNITS_MUL | UNIT_VLUT},
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[midgard_alu_op_fmin] = {"fmin", UNITS_MUL | UNITS_ADD},
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[midgard_alu_op_fmax] = {"fmax", UNITS_MUL | UNITS_ADD},
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[midgard_alu_op_imin] = {"imin", UNITS_MOST},
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[midgard_alu_op_imax] = {"imax", UNITS_MOST},
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[midgard_alu_op_umin] = {"umin", UNITS_MOST},
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[midgard_alu_op_umax] = {"umax", UNITS_MOST},
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[midgard_alu_op_fadd] = {"fadd", UNITS_ADD | OP_COMMUTES},
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[midgard_alu_op_fmul] = {"fmul", UNITS_MUL | UNIT_VLUT | OP_COMMUTES},
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[midgard_alu_op_fmin] = {"fmin", UNITS_MUL | UNITS_ADD | OP_COMMUTES},
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[midgard_alu_op_fmax] = {"fmax", UNITS_MUL | UNITS_ADD | OP_COMMUTES},
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[midgard_alu_op_imin] = {"imin", UNITS_MOST | OP_COMMUTES},
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[midgard_alu_op_imax] = {"imax", UNITS_MOST | OP_COMMUTES},
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[midgard_alu_op_umin] = {"umin", UNITS_MOST | OP_COMMUTES},
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[midgard_alu_op_umax] = {"umax", UNITS_MOST | OP_COMMUTES},
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[midgard_alu_op_fmov] = {"fmov", UNITS_ALL | QUIRK_FLIPPED_R24},
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[midgard_alu_op_fround] = {"fround", UNITS_ADD},
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[midgard_alu_op_froundeven] = {"froundeven", UNITS_ADD},
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@ -169,24 +172,24 @@ static struct {
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/* Though they output a scalar, they need to run on a vector unit
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* since they process vectors */
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[midgard_alu_op_fdot3] = {"fdot3", UNIT_VMUL | OP_CHANNEL_COUNT(3)},
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[midgard_alu_op_fdot3r] = {"fdot3r", UNIT_VMUL | OP_CHANNEL_COUNT(3)},
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[midgard_alu_op_fdot4] = {"fdot4", UNIT_VMUL | OP_CHANNEL_COUNT(4)},
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[midgard_alu_op_fdot3] = {"fdot3", UNIT_VMUL | OP_CHANNEL_COUNT(3) | OP_COMMUTES},
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[midgard_alu_op_fdot3r] = {"fdot3r", UNIT_VMUL | OP_CHANNEL_COUNT(3) | OP_COMMUTES},
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[midgard_alu_op_fdot4] = {"fdot4", UNIT_VMUL | OP_CHANNEL_COUNT(4) | OP_COMMUTES},
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/* Incredibly, iadd can run on vmul, etc */
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[midgard_alu_op_iadd] = {"iadd", UNITS_MOST},
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[midgard_alu_op_iadd] = {"iadd", UNITS_MOST | OP_COMMUTES},
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[midgard_alu_op_iabs] = {"iabs", UNITS_MOST},
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[midgard_alu_op_isub] = {"isub", UNITS_MOST},
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[midgard_alu_op_imul] = {"imul", UNITS_MUL},
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[midgard_alu_op_imul] = {"imul", UNITS_MUL | OP_COMMUTES},
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[midgard_alu_op_imov] = {"imov", UNITS_MOST | QUIRK_FLIPPED_R24},
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/* For vector comparisons, use ball etc */
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[midgard_alu_op_feq] = {"feq", UNITS_MOST},
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[midgard_alu_op_fne] = {"fne", UNITS_MOST},
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[midgard_alu_op_feq] = {"feq", UNITS_MOST | OP_COMMUTES},
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[midgard_alu_op_fne] = {"fne", UNITS_MOST | OP_COMMUTES},
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[midgard_alu_op_fle] = {"fle", UNITS_MOST},
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[midgard_alu_op_flt] = {"flt", UNITS_MOST},
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[midgard_alu_op_ieq] = {"ieq", UNITS_MOST},
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[midgard_alu_op_ine] = {"ine", UNITS_MOST},
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[midgard_alu_op_ieq] = {"ieq", UNITS_MOST | OP_COMMUTES},
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[midgard_alu_op_ine] = {"ine", UNITS_MOST | OP_COMMUTES},
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[midgard_alu_op_ilt] = {"ilt", UNITS_MOST},
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[midgard_alu_op_ile] = {"ile", UNITS_MOST},
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[midgard_alu_op_ult] = {"ult", UNITS_MOST},
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@ -213,10 +216,10 @@ static struct {
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[midgard_alu_op_fcos] = {"fcos", UNIT_VLUT},
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/* XXX: Test case where it's right on smul but not sadd */
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[midgard_alu_op_iand] = {"iand", UNITS_ADD},
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[midgard_alu_op_iand] = {"iand", UNITS_ADD | OP_COMMUTES},
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[midgard_alu_op_ior] = {"ior", UNITS_ADD},
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[midgard_alu_op_ixor] = {"ixor", UNITS_ADD},
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[midgard_alu_op_ior] = {"ior", UNITS_ADD | OP_COMMUTES},
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[midgard_alu_op_ixor] = {"ixor", UNITS_ADD | OP_COMMUTES},
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[midgard_alu_op_ilzcnt] = {"ilzcnt", UNITS_ADD},
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[midgard_alu_op_ibitcount8] = {"ibitcount8", UNITS_ADD},
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[midgard_alu_op_inot] = {"inot", UNITS_MOST},
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@ -224,12 +227,12 @@ static struct {
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[midgard_alu_op_iasr] = {"iasr", UNITS_ADD},
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[midgard_alu_op_ilsr] = {"ilsr", UNITS_ADD},
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[midgard_alu_op_fball_eq] = {"fball_eq", UNITS_VECTOR},
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[midgard_alu_op_fbany_neq] = {"fbany_neq", UNITS_VECTOR},
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[midgard_alu_op_iball_eq] = {"iball_eq", UNITS_VECTOR},
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[midgard_alu_op_iball_neq] = {"iball_neq", UNITS_VECTOR},
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[midgard_alu_op_ibany_eq] = {"ibany_eq", UNITS_VECTOR},
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[midgard_alu_op_ibany_neq] = {"ibany_neq", UNITS_VECTOR},
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[midgard_alu_op_fball_eq] = {"fball_eq", UNITS_VECTOR | OP_COMMUTES},
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[midgard_alu_op_fbany_neq] = {"fbany_neq", UNITS_VECTOR | OP_COMMUTES},
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[midgard_alu_op_iball_eq] = {"iball_eq", UNITS_VECTOR | OP_COMMUTES},
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[midgard_alu_op_iball_neq] = {"iball_neq", UNITS_VECTOR | OP_COMMUTES},
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[midgard_alu_op_ibany_eq] = {"ibany_eq", UNITS_VECTOR | OP_COMMUTES},
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[midgard_alu_op_ibany_neq] = {"ibany_neq", UNITS_VECTOR | OP_COMMUTES},
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/* These instructions are not yet emitted by the compiler, so
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* don't speculate about units yet */
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@ -246,8 +249,8 @@ static struct {
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[midgard_alu_op_ibany_lte] = {"ibany_lte", 0},
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[midgard_alu_op_freduce] = {"freduce", 0},
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[midgard_alu_op_bball_eq] = {"bball_eq", 0},
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[midgard_alu_op_bbany_neq] = {"bball_eq", 0},
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[midgard_alu_op_bball_eq] = {"bball_eq", 0 | OP_COMMUTES},
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[midgard_alu_op_bbany_neq] = {"bball_eq", 0 | OP_COMMUTES},
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[midgard_alu_op_fatan2_pt1] = {"fatan2_pt1", 0},
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[midgard_alu_op_fatan_pt2] = {"fatan_pt2", 0},
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};
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@ -2948,34 +2948,21 @@ embedded_to_inline_constant(compiler_context *ctx)
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int op = ins->alu.op;
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if (ins->ssa_args.src0 == SSA_FIXED_REGISTER(REGISTER_CONSTANT)) {
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/* Flip based on op. Fallthrough intentional */
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switch (op) {
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/* These ops require an operational change to flip their arguments TODO */
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/* These ops require an operational change to flip
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* their arguments TODO */
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case midgard_alu_op_flt:
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case midgard_alu_op_fle:
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case midgard_alu_op_ilt:
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case midgard_alu_op_ile:
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case midgard_alu_op_fcsel:
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case midgard_alu_op_icsel:
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case midgard_alu_op_isub:
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DBG("Missed non-commutative flip (%s)\n", alu_opcode_props[op].name);
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default:
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break;
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}
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/* These ops are commutative and Just Flip */
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case midgard_alu_op_fne:
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case midgard_alu_op_fadd:
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case midgard_alu_op_fmul:
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case midgard_alu_op_fmin:
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case midgard_alu_op_fmax:
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case midgard_alu_op_iadd:
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case midgard_alu_op_imul:
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case midgard_alu_op_feq:
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case midgard_alu_op_ieq:
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case midgard_alu_op_ine:
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case midgard_alu_op_iand:
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case midgard_alu_op_ior:
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case midgard_alu_op_ixor:
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if (alu_opcode_props[op].props & OP_COMMUTES) {
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/* Flip the SSA numbers */
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ins->ssa_args.src0 = ins->ssa_args.src1;
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ins->ssa_args.src1 = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
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@ -2987,9 +2974,6 @@ embedded_to_inline_constant(compiler_context *ctx)
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src_temp = ins->alu.src2;
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ins->alu.src2 = ins->alu.src1;
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ins->alu.src1 = src_temp;
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default:
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break;
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}
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}
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