diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c index 622be2ed039..8e1f0388455 100644 --- a/src/amd/common/ac_gpu_info.c +++ b/src/amd/common/ac_gpu_info.c @@ -567,6 +567,7 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info, } else { info->tcc_cache_line_size = 64; } + info->mc_arb_ramcfg = amdinfo->mc_arb_ramcfg; info->gb_addr_config = amdinfo->gb_addr_cfg; if (info->chip_class >= GFX9) { info->num_tile_pipes = 1 << G_0098F8_NUM_PIPES(amdinfo->gb_addr_cfg); diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h index adc961ad32c..86119d64a07 100644 --- a/src/amd/common/ac_gpu_info.h +++ b/src/amd/common/ac_gpu_info.h @@ -188,6 +188,7 @@ struct radeon_info { uint32_t r600_gb_backend_map; /* R600 harvest config */ bool r600_gb_backend_map_valid; uint32_t r600_num_banks; + uint32_t mc_arb_ramcfg; uint32_t gb_addr_config; uint32_t pa_sc_tile_steering_override; /* CLEAR_STATE also sets this */ uint32_t max_render_backends; /* number of render backends incl. disabled ones */ diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c index 619b655250f..0f183ae93a2 100644 --- a/src/amd/common/ac_surface.c +++ b/src/amd/common/ac_surface.c @@ -42,7 +42,6 @@ #include "util/u_math.h" #include "util/u_memory.h" -#include #include #include #include @@ -593,7 +592,7 @@ static ADDR_E_RETURNCODE ADDR_API freeSysMem(const ADDR_FREESYSMEM_INPUT *pInput } struct ac_addrlib *ac_addrlib_create(const struct radeon_info *info, - const struct amdgpu_gpu_info *amdinfo, uint64_t *max_alignment) + uint64_t *max_alignment) { ADDR_CREATE_INPUT addrCreateInput = {0}; ADDR_CREATE_OUTPUT addrCreateOutput = {0}; @@ -605,7 +604,7 @@ struct ac_addrlib *ac_addrlib_create(const struct radeon_info *info, addrCreateInput.size = sizeof(ADDR_CREATE_INPUT); addrCreateOutput.size = sizeof(ADDR_CREATE_OUTPUT); - regValue.gbAddrConfig = amdinfo->gb_addr_cfg; + regValue.gbAddrConfig = info->gb_addr_config; createFlags.value = 0; addrCreateInput.chipFamily = info->family_id; @@ -617,18 +616,18 @@ struct ac_addrlib *ac_addrlib_create(const struct radeon_info *info, if (addrCreateInput.chipFamily >= FAMILY_AI) { addrCreateInput.chipEngine = CIASICIDGFXENGINE_ARCTICISLAND; } else { - regValue.noOfBanks = amdinfo->mc_arb_ramcfg & 0x3; - regValue.noOfRanks = (amdinfo->mc_arb_ramcfg & 0x4) >> 2; + regValue.noOfBanks = info->mc_arb_ramcfg & 0x3; + regValue.noOfRanks = (info->mc_arb_ramcfg & 0x4) >> 2; - regValue.backendDisables = amdinfo->enabled_rb_pipes_mask; - regValue.pTileConfig = amdinfo->gb_tile_mode; - regValue.noOfEntries = ARRAY_SIZE(amdinfo->gb_tile_mode); + regValue.backendDisables = info->enabled_rb_mask; + regValue.pTileConfig = info->si_tile_mode_array; + regValue.noOfEntries = ARRAY_SIZE(info->si_tile_mode_array); if (addrCreateInput.chipFamily == FAMILY_SI) { regValue.pMacroTileConfig = NULL; regValue.noOfMacroEntries = 0; } else { - regValue.pMacroTileConfig = amdinfo->gb_macro_tile_mode; - regValue.noOfMacroEntries = ARRAY_SIZE(amdinfo->gb_macro_tile_mode); + regValue.pMacroTileConfig = info->cik_macrotile_mode_array; + regValue.noOfMacroEntries = ARRAY_SIZE(info->cik_macrotile_mode_array); } createFlags.useTileIndex = 1; diff --git a/src/amd/common/ac_surface.h b/src/amd/common/ac_surface.h index 424bbd12408..ebec13d53ba 100644 --- a/src/amd/common/ac_surface.h +++ b/src/amd/common/ac_surface.h @@ -296,9 +296,7 @@ struct ac_surf_config { unsigned is_cube : 1; }; -struct ac_addrlib *ac_addrlib_create(const struct radeon_info *info, - const struct amdgpu_gpu_info *amdinfo, - uint64_t *max_alignment); +struct ac_addrlib *ac_addrlib_create(const struct radeon_info *info, uint64_t *max_alignment); void ac_addrlib_destroy(struct ac_addrlib *addrlib); void *ac_addrlib_get_handle(struct ac_addrlib *addrlib); diff --git a/src/amd/common/ac_surface_modifier_test.c b/src/amd/common/ac_surface_modifier_test.c index b66351cf57c..c579f5bd1ee 100644 --- a/src/amd/common/ac_surface_modifier_test.c +++ b/src/amd/common/ac_surface_modifier_test.c @@ -292,7 +292,6 @@ void generate_hash(struct ac_addrlib *ac_addrlib, } static void test_modifier(const struct radeon_info *info, - const struct amdgpu_gpu_info *amdinfo, const char *name, struct ac_addrlib *addrlib, uint64_t modifier, @@ -386,21 +385,21 @@ static void test_modifier(const struct radeon_info *info, uint64_t dcc_align = 1; unsigned block_bits; if (info->chip_class >= GFX10) { - unsigned num_pipes = G_0098F8_NUM_PIPES(amdinfo->gb_addr_cfg); + unsigned num_pipes = G_0098F8_NUM_PIPES(info->gb_addr_config); if (info->chip_class == GFX10_3 && - G_0098F8_NUM_PKRS(amdinfo->gb_addr_cfg) == num_pipes && num_pipes > 1) + G_0098F8_NUM_PKRS(info->gb_addr_config) == num_pipes && num_pipes > 1) ++num_pipes; block_bits = 16 + num_pipes + - G_0098F8_PIPE_INTERLEAVE_SIZE_GFX9(amdinfo->gb_addr_cfg); + G_0098F8_PIPE_INTERLEAVE_SIZE_GFX9(info->gb_addr_config); block_bits = MAX2(block_bits, 20); dcc_align = MAX2(4096, 256 << (num_pipes + - G_0098F8_PIPE_INTERLEAVE_SIZE_GFX9(amdinfo->gb_addr_cfg))); + G_0098F8_PIPE_INTERLEAVE_SIZE_GFX9(info->gb_addr_config))); } else { block_bits = 18 + - G_0098F8_NUM_RB_PER_SE(amdinfo->gb_addr_cfg) + - G_0098F8_NUM_SHADER_ENGINES_GFX9(amdinfo->gb_addr_cfg); + G_0098F8_NUM_RB_PER_SE(info->gb_addr_config) + + G_0098F8_NUM_SHADER_ENGINES_GFX9(info->gb_addr_config); block_bits = MAX2(block_bits, 20); dcc_align = 65536; } @@ -428,11 +427,7 @@ static void test_modifier(const struct radeon_info *info, static void run_gpu_test(struct u_vector *test_entries, const char *name, const struct radeon_info *info) { - struct amdgpu_gpu_info amdinfo = { - .gb_addr_cfg = info->gb_addr_config - }; - - struct ac_addrlib *addrlib = ac_addrlib_create(info, &amdinfo, NULL); + struct ac_addrlib *addrlib = ac_addrlib_create(info, NULL); assert(addrlib); const struct ac_modifier_options options = { @@ -455,7 +450,7 @@ static void run_gpu_test(struct u_vector *test_entries, const char *name, const ac_get_supported_modifiers(info, &options, formats[j], &mod_count, modifiers); for (unsigned i = 0; i < mod_count; ++i) { - test_modifier(info, &amdinfo, name, addrlib, modifiers[i], formats[j], test_entries); + test_modifier(info, name, addrlib, modifiers[i], formats[j], test_entries); } free(modifiers); diff --git a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_winsys.c b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_winsys.c index c1a738a2b7f..7686ce406d8 100644 --- a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_winsys.c +++ b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_winsys.c @@ -61,7 +61,7 @@ do_winsys_init(struct radv_amdgpu_winsys *ws, int fd) ws->info.use_display_dcc_unaligned = false; ws->info.use_display_dcc_with_retile_blit = false; - ws->addrlib = ac_addrlib_create(&ws->info, &ws->amdinfo, &ws->info.max_alignment); + ws->addrlib = ac_addrlib_create(&ws->info, &ws->info.max_alignment); if (!ws->addrlib) { fprintf(stderr, "amdgpu: Cannot create addrlib.\n"); return false; diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c index a339c517235..75a6605f294 100644 --- a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c +++ b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c @@ -102,7 +102,7 @@ static bool do_winsys_init(struct amdgpu_winsys *ws, handle_env_var_force_family(ws); - ws->addrlib = ac_addrlib_create(&ws->info, &ws->amdinfo, &ws->info.max_alignment); + ws->addrlib = ac_addrlib_create(&ws->info, &ws->info.max_alignment); if (!ws->addrlib) { fprintf(stderr, "amdgpu: Cannot create addrlib.\n"); goto fail;