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v3d/v3dv: define performance counters in common
Both OpenGL and Vulkan drivers share the same performance counters. Let's move them to a common place instead of duplicating. Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com> Reviewed-by: Iago Toral Quiroga <itoral@igalia.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21420>
This commit is contained in:
Juan A. Suarez Romero
Marge Bot
parent
161e3f29f4
commit
baff509924
3 changed files with 135 additions and 190 deletions
121
src/broadcom/common/v3d_performance_counters.h
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121
src/broadcom/common/v3d_performance_counters.h
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@ -0,0 +1,121 @@
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/*
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* Copyright © 2023 Raspberry Pi Ltd
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#ifndef V3D_PERFORMANCE_COUNTERS_H
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#define V3D_PERFORMANCE_COUNTERS_H
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#define V3D_PERFCNT_CATEGORY 0
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#define V3D_PERFCNT_NAME 1
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#define V3D_PERFCNT_DESCRIPTION 2
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static const char *v3d_performance_counters[][3] = {
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{"FEP", "FEP-valid-primitives-no-rendered-pixels", "[FEP] Valid primitives that result in no rendered pixels, for all rendered tiles"},
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{"FEP", "FEP-valid-primitives-rendered-pixels", "[FEP] Valid primitives for all rendered tiles (primitives may be counted in more than one tile)"},
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{"FEP", "FEP-clipped-quads", "[FEP] Early-Z/Near/Far clipped quads"},
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{"FEP", "FEP-valid-quads", "[FEP] Valid quads"},
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{"TLB", "TLB-quads-not-passing-stencil-test", "[TLB] Quads with no pixels passing the stencil test"},
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{"TLB", "TLB-quads-not-passing-z-and-stencil-test", "[TLB] Quads with no pixels passing the Z and stencil tests"},
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{"TLB", "TLB-quads-passing-z-and-stencil-test", "[TLB] Quads with any pixels passing the Z and stencil tests"},
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{"TLB", "TLB-quads-with-zero-coverage", "[TLB] Quads with all pixels having zero coverage"},
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{"TLB", "TLB-quads-with-non-zero-coverage", "[TLB] Quads with any pixels having non-zero coverage"},
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{"TLB", "TLB-quads-written-to-color-buffer", "[TLB] Quads with valid pixels written to colour buffer"},
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{"PTB", "PTB-primitives-discarded-outside-viewport", "[PTB] Primitives discarded by being outside the viewport"},
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{"PTB", "PTB-primitives-need-clipping", "[PTB] Primitives that need clipping"},
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{"PTB", "PTB-primitives-discared-reversed", "[PTB] Primitives that are discarded because they are reversed"},
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{"QPU", "QPU-total-idle-clk-cycles", "[QPU] Total idle clock cycles for all QPUs"},
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{"QPU", "QPU-total-active-clk-cycles-vertex-coord-shading", "[QPU] Total active clock cycles for all QPUs doing vertex/coordinate/user shading (counts only when QPU is not stalled)"},
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{"QPU", "QPU-total-active-clk-cycles-fragment-shading", "[QPU] Total active clock cycles for all QPUs doing fragment shading (counts only when QPU is not stalled)"},
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{"QPU", "QPU-total-clk-cycles-executing-valid-instr", "[QPU] Total clock cycles for all QPUs executing valid instructions"},
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{"QPU", "QPU-total-clk-cycles-waiting-TMU", "[QPU] Total clock cycles for all QPUs stalled waiting for TMUs only (counter won't increment if QPU also stalling for another reason)"},
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{"QPU", "QPU-total-clk-cycles-waiting-scoreboard", "[QPU] Total clock cycles for all QPUs stalled waiting for Scoreboard only (counter won't increment if QPU also stalling for another reason)"},
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{"QPU", "QPU-total-clk-cycles-waiting-varyings", "[QPU] Total clock cycles for all QPUs stalled waiting for Varyings only (counter won't increment if QPU also stalling for another reason)"},
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{"QPU", "QPU-total-instr-cache-hit", "[QPU] Total instruction cache hits for all slices"},
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{"QPU", "QPU-total-instr-cache-miss", "[QPU] Total instruction cache misses for all slices"},
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{"QPU", "QPU-total-uniform-cache-hit", "[QPU] Total uniforms cache hits for all slices"},
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{"QPU", "QPU-total-uniform-cache-miss", "[QPU] Total uniforms cache misses for all slices"},
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{"TMU", "TMU-total-text-quads-access", "[TMU] Total texture cache accesses"},
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{"TMU", "TMU-total-text-cache-miss", "[TMU] Total texture cache misses (number of fetches from memory/L2cache)"},
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{"VPM", "VPM-total-clk-cycles-VDW-stalled", "[VPM] Total clock cycles VDW is stalled waiting for VPM access"},
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{"VPM", "VPM-total-clk-cycles-VCD-stalled", "[VPM] Total clock cycles VCD is stalled waiting for VPM access"},
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{"CLE", "CLE-bin-thread-active-cycles", "[CLE] Bin thread active cycles"},
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{"CLE", "CLE-render-thread-active-cycles", "[CLE] Render thread active cycles"},
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{"L2T", "L2T-total-cache-hit", "[L2T] Total Level 2 cache hits"},
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{"L2T", "L2T-total-cache-miss", "[L2T] Total Level 2 cache misses"},
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{"CORE", "cycle-count", "[CORE] Cycle counter"},
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{"QPU", "QPU-total-clk-cycles-waiting-vertex-coord-shading", "[QPU] Total stalled clock cycles for all QPUs doing vertex/coordinate/user shading"},
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{"QPU", "QPU-total-clk-cycles-waiting-fragment-shading", "[QPU] Total stalled clock cycles for all QPUs doing fragment shading"},
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{"PTB", "PTB-primitives-binned", "[PTB] Total primitives binned"},
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{"AXI", "AXI-writes-seen-watch-0", "[AXI] Writes seen by watch 0"},
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{"AXI", "AXI-reads-seen-watch-0", "[AXI] Reads seen by watch 0"},
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{"AXI", "AXI-writes-stalled-seen-watch-0", "[AXI] Write stalls seen by watch 0"},
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{"AXI", "AXI-reads-stalled-seen-watch-0", "[AXI] Read stalls seen by watch 0"},
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{"AXI", "AXI-write-bytes-seen-watch-0", "[AXI] Total bytes written seen by watch 0"},
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{"AXI", "AXI-read-bytes-seen-watch-0", "[AXI] Total bytes read seen by watch 0"},
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{"AXI", "AXI-writes-seen-watch-1", "[AXI] Writes seen by watch 1"},
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{"AXI", "AXI-reads-seen-watch-1", "[AXI] Reads seen by watch 1"},
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{"AXI", "AXI-writes-stalled-seen-watch-1", "[AXI] Write stalls seen by watch 1"},
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{"AXI", "AXI-reads-stalled-seen-watch-1", "[AXI] Read stalls seen by watch 1"},
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{"AXI", "AXI-write-bytes-seen-watch-1", "[AXI] Total bytes written seen by watch 1"},
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{"AXI", "AXI-read-bytes-seen-watch-1", "[AXI] Total bytes read seen by watch 1"},
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{"TLB", "TLB-partial-quads-written-to-color-buffer", "[TLB] Partial quads written to the colour buffer"},
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{"TMU", "TMU-total-config-access", "[TMU] Total config accesses"},
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{"L2T", "L2T-no-id-stalled", "[L2T] No ID stall"},
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{"L2T", "L2T-command-queue-stalled", "[L2T] Command queue full stall"},
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{"L2T", "L2T-TMU-writes", "[L2T] TMU write accesses"},
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{"TMU", "TMU-active-cycles", "[TMU] Active cycles"},
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{"TMU", "TMU-stalled-cycles", "[TMU] Stalled cycles"},
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{"CLE", "CLE-thread-active-cycles", "[CLE] Bin or render thread active cycles"},
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{"L2T", "L2T-TMU-reads", "[L2T] TMU read accesses"},
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{"L2T", "L2T-CLE-reads", "[L2T] CLE read accesses"},
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{"L2T", "L2T-VCD-reads", "[L2T] VCD read accesses"},
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{"L2T", "L2T-TMU-config-reads", "[L2T] TMU CFG read accesses"},
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{"L2T", "L2T-SLC0-reads", "[L2T] SLC0 read accesses"},
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{"L2T", "L2T-SLC1-reads", "[L2T] SLC1 read accesses"},
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{"L2T", "L2T-SLC2-reads", "[L2T] SLC2 read accesses"},
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{"L2T", "L2T-TMU-write-miss", "[L2T] TMU write misses"},
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{"L2T", "L2T-TMU-read-miss", "[L2T] TMU read misses"},
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{"L2T", "L2T-CLE-read-miss", "[L2T] CLE read misses"},
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{"L2T", "L2T-VCD-read-miss", "[L2T] VCD read misses"},
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{"L2T", "L2T-TMU-config-read-miss", "[L2T] TMU CFG read misses"},
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{"L2T", "L2T-SLC0-read-miss", "[L2T] SLC0 read misses"},
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{"L2T", "L2T-SLC1-read-miss", "[L2T] SLC1 read misses"},
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{"L2T", "L2T-SLC2-read-miss", "[L2T] SLC2 read misses"},
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{"CORE", "core-memory-writes", "[CORE] Total memory writes"},
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{"L2T", "L2T-memory-writes", "[L2T] Total memory writes"},
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{"PTB", "PTB-memory-writes", "[PTB] Total memory writes"},
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{"TLB", "TLB-memory-writes", "[TLB] Total memory writes"},
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{"CORE", "core-memory-reads", "[CORE] Total memory reads"},
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{"L2T", "L2T-memory-reads", "[L2T] Total memory reads"},
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{"PTB", "PTB-memory-reads", "[PTB] Total memory reads"},
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{"PSE", "PSE-memory-reads", "[PSE] Total memory reads"},
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{"TLB", "TLB-memory-reads", "[TLB] Total memory reads"},
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{"GMP", "GMP-memory-reads", "[GMP] Total memory reads"},
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{"PTB", "PTB-memory-words-writes", "[PTB] Total memory words written"},
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{"TLB", "TLB-memory-words-writes", "[TLB] Total memory words written"},
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{"PSE", "PSE-memory-words-reads", "[PSE] Total memory words read"},
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{"TLB", "TLB-memory-words-reads", "[TLB] Total memory words read"},
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{"TMU", "TMU-MRU-hits", "[TMU] Total MRU hits"},
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{"CORE", "compute-active-cycles", "[CORE] Compute active cycles"},
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};
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#endif
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@ -23,99 +23,10 @@
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#include "v3dv_private.h"
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#include "common/v3d_performance_counters.h"
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#include "util/timespec.h"
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#include "compiler/nir/nir_builder.h"
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static const char *v3dv_counters[][3] = {
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{"FEP", "FEP-valid-primitives-no-rendered-pixels", "[FEP] Valid primitives that result in no rendered pixels, for all rendered tiles"},
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{"FEP", "FEP-valid-primitives-rendered-pixels", "[FEP] Valid primitives for all rendered tiles (primitives may be counted in more than one tile)"},
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{"FEP", "FEP-clipped-quads", "[FEP] Early-Z/Near/Far clipped quads"},
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{"FEP", "FEP-valid-quads", "[FEP] Valid quads"},
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{"TLB", "TLB-quads-not-passing-stencil-test", "[TLB] Quads with no pixels passing the stencil test"},
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{"TLB", "TLB-quads-not-passing-z-and-stencil-test", "[TLB] Quads with no pixels passing the Z and stencil tests"},
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{"TLB", "TLB-quads-passing-z-and-stencil-test", "[TLB] Quads with any pixels passing the Z and stencil tests"},
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{"TLB", "TLB-quads-with-zero-coverage", "[TLB] Quads with all pixels having zero coverage"},
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{"TLB", "TLB-quads-with-non-zero-coverage", "[TLB] Quads with any pixels having non-zero coverage"},
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{"TLB", "TLB-quads-written-to-color-buffer", "[TLB] Quads with valid pixels written to colour buffer"},
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{"PTB", "PTB-primitives-discarded-outside-viewport", "[PTB] Primitives discarded by being outside the viewport"},
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{"PTB", "PTB-primitives-need-clipping", "[PTB] Primitives that need clipping"},
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{"PTB", "PTB-primitives-discared-reversed", "[PTB] Primitives that are discarded because they are reversed"},
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{"QPU", "QPU-total-idle-clk-cycles", "[QPU] Total idle clock cycles for all QPUs"},
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{"QPU", "QPU-total-active-clk-cycles-vertex-coord-shading", "[QPU] Total active clock cycles for all QPUs doing vertex/coordinate/user shading (counts only when QPU is not stalled)"},
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{"QPU", "QPU-total-active-clk-cycles-fragment-shading", "[QPU] Total active clock cycles for all QPUs doing fragment shading (counts only when QPU is not stalled)"},
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{"QPU", "QPU-total-clk-cycles-executing-valid-instr", "[QPU] Total clock cycles for all QPUs executing valid instructions"},
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{"QPU", "QPU-total-clk-cycles-waiting-TMU", "[QPU] Total clock cycles for all QPUs stalled waiting for TMUs only (counter won't increment if QPU also stalling for another reason)"},
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{"QPU", "QPU-total-clk-cycles-waiting-scoreboard", "[QPU] Total clock cycles for all QPUs stalled waiting for Scoreboard only (counter won't increment if QPU also stalling for another reason)"},
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{"QPU", "QPU-total-clk-cycles-waiting-varyings", "[QPU] Total clock cycles for all QPUs stalled waiting for Varyings only (counter won't increment if QPU also stalling for another reason)"},
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{"QPU", "QPU-total-instr-cache-hit", "[QPU] Total instruction cache hits for all slices"},
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{"QPU", "QPU-total-instr-cache-miss", "[QPU] Total instruction cache misses for all slices"},
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{"QPU", "QPU-total-uniform-cache-hit", "[QPU] Total uniforms cache hits for all slices"},
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{"QPU", "QPU-total-uniform-cache-miss", "[QPU] Total uniforms cache misses for all slices"},
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{"TMU", "TMU-total-text-quads-access", "[TMU] Total texture cache accesses"},
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{"TMU", "TMU-total-text-cache-miss", "[TMU] Total texture cache misses (number of fetches from memory/L2cache)"},
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{"VPM", "VPM-total-clk-cycles-VDW-stalled", "[VPM] Total clock cycles VDW is stalled waiting for VPM access"},
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{"VPM", "VPM-total-clk-cycles-VCD-stalled", "[VPM] Total clock cycles VCD is stalled waiting for VPM access"},
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{"CLE", "CLE-bin-thread-active-cycles", "[CLE] Bin thread active cycles"},
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{"CLE", "CLE-render-thread-active-cycles", "[CLE] Render thread active cycles"},
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{"L2T", "L2T-total-cache-hit", "[L2T] Total Level 2 cache hits"},
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{"L2T", "L2T-total-cache-miss", "[L2T] Total Level 2 cache misses"},
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{"CORE", "cycle-count", "[CORE] Cycle counter"},
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{"QPU", "QPU-total-clk-cycles-waiting-vertex-coord-shading", "[QPU] Total stalled clock cycles for all QPUs doing vertex/coordinate/user shading"},
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{"QPU", "QPU-total-clk-cycles-waiting-fragment-shading", "[QPU] Total stalled clock cycles for all QPUs doing fragment shading"},
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{"PTB", "PTB-primitives-binned", "[PTB] Total primitives binned"},
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{"AXI", "AXI-writes-seen-watch-0", "[AXI] Writes seen by watch 0"},
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{"AXI", "AXI-reads-seen-watch-0", "[AXI] Reads seen by watch 0"},
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{"AXI", "AXI-writes-stalled-seen-watch-0", "[AXI] Write stalls seen by watch 0"},
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{"AXI", "AXI-reads-stalled-seen-watch-0", "[AXI] Read stalls seen by watch 0"},
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{"AXI", "AXI-write-bytes-seen-watch-0", "[AXI] Total bytes written seen by watch 0"},
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{"AXI", "AXI-read-bytes-seen-watch-0", "[AXI] Total bytes read seen by watch 0"},
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{"AXI", "AXI-writes-seen-watch-1", "[AXI] Writes seen by watch 1"},
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{"AXI", "AXI-reads-seen-watch-1", "[AXI] Reads seen by watch 1"},
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{"AXI", "AXI-writes-stalled-seen-watch-1", "[AXI] Write stalls seen by watch 1"},
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{"AXI", "AXI-reads-stalled-seen-watch-1", "[AXI] Read stalls seen by watch 1"},
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{"AXI", "AXI-write-bytes-seen-watch-1", "[AXI] Total bytes written seen by watch 1"},
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{"AXI", "AXI-read-bytes-seen-watch-1", "[AXI] Total bytes read seen by watch 1"},
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{"TLB", "TLB-partial-quads-written-to-color-buffer", "[TLB] Partial quads written to the colour buffer"},
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{"TMU", "TMU-total-config-access", "[TMU] Total config accesses"},
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{"L2T", "L2T-no-id-stalled", "[L2T] No ID stall"},
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{"L2T", "L2T-command-queue-stalled", "[L2T] Command queue full stall"},
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{"L2T", "L2T-TMU-writes", "[L2T] TMU write accesses"},
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{"TMU", "TMU-active-cycles", "[TMU] Active cycles"},
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{"TMU", "TMU-stalled-cycles", "[TMU] Stalled cycles"},
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{"CLE", "CLE-thread-active-cycles", "[CLE] Bin or render thread active cycles"},
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{"L2T", "L2T-TMU-reads", "[L2T] TMU read accesses"},
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{"L2T", "L2T-CLE-reads", "[L2T] CLE read accesses"},
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{"L2T", "L2T-VCD-reads", "[L2T] VCD read accesses"},
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{"L2T", "L2T-TMU-config-reads", "[L2T] TMU CFG read accesses"},
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{"L2T", "L2T-SLC0-reads", "[L2T] SLC0 read accesses"},
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{"L2T", "L2T-SLC1-reads", "[L2T] SLC1 read accesses"},
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{"L2T", "L2T-SLC2-reads", "[L2T] SLC2 read accesses"},
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{"L2T", "L2T-TMU-write-miss", "[L2T] TMU write misses"},
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{"L2T", "L2T-TMU-read-miss", "[L2T] TMU read misses"},
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{"L2T", "L2T-CLE-read-miss", "[L2T] CLE read misses"},
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{"L2T", "L2T-VCD-read-miss", "[L2T] VCD read misses"},
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{"L2T", "L2T-TMU-config-read-miss", "[L2T] TMU CFG read misses"},
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{"L2T", "L2T-SLC0-read-miss", "[L2T] SLC0 read misses"},
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{"L2T", "L2T-SLC1-read-miss", "[L2T] SLC1 read misses"},
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{"L2T", "L2T-SLC2-read-miss", "[L2T] SLC2 read misses"},
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{"CORE", "core-memory-writes", "[CORE] Total memory writes"},
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{"L2T", "L2T-memory-writes", "[L2T] Total memory writes"},
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{"PTB", "PTB-memory-writes", "[PTB] Total memory writes"},
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{"TLB", "TLB-memory-writes", "[TLB] Total memory writes"},
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{"CORE", "core-memory-reads", "[CORE] Total memory reads"},
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{"L2T", "L2T-memory-reads", "[L2T] Total memory reads"},
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{"PTB", "PTB-memory-reads", "[PTB] Total memory reads"},
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{"PSE", "PSE-memory-reads", "[PSE] Total memory reads"},
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{"TLB", "TLB-memory-reads", "[TLB] Total memory reads"},
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{"GMP", "GMP-memory-reads", "[GMP] Total memory reads"},
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{"PTB", "PTB-memory-words-writes", "[PTB] Total memory words written"},
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{"TLB", "TLB-memory-words-writes", "[TLB] Total memory words written"},
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{"PSE", "PSE-memory-words-reads", "[PSE] Total memory words read"},
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{"TLB", "TLB-memory-words-reads", "[TLB] Total memory words read"},
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{"TMU", "TMU-MRU-hits", "[TMU] Total MRU hits"},
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{"CORE", "compute-active-cycles", "[CORE] Compute active cycles"},
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};
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static void
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kperfmon_create(struct v3dv_device *device,
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struct v3dv_query_pool *pool,
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@ -1380,14 +1291,15 @@ v3dv_EnumeratePhysicalDeviceQueueFamilyPerformanceQueryCountersKHR(
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VK_OUTARRAY_MAKE_TYPED(VkPerformanceCounterDescriptionKHR,
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out_desc, pCounterDescriptions, &desc_count);
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for (int i = 0; i < ARRAY_SIZE(v3dv_counters); i++) {
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for (int i = 0; i < ARRAY_SIZE(v3d_performance_counters); i++) {
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vk_outarray_append_typed(VkPerformanceCounterKHR, &out, counter) {
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counter->unit = VK_PERFORMANCE_COUNTER_UNIT_GENERIC_KHR;
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counter->scope = VK_PERFORMANCE_COUNTER_SCOPE_COMMAND_KHR;
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counter->storage = VK_PERFORMANCE_COUNTER_STORAGE_UINT64_KHR;
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unsigned char sha1_result[20];
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_mesa_sha1_compute(v3dv_counters[i][1], strlen(v3dv_counters[i][1]),
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||||
_mesa_sha1_compute(v3d_performance_counters[i][V3D_PERFCNT_NAME],
|
||||
strlen(v3d_performance_counters[i][V3D_PERFCNT_NAME]),
|
||||
sha1_result);
|
||||
|
||||
memcpy(counter->uuid, sha1_result, sizeof(counter->uuid));
|
||||
|
|
@ -1397,11 +1309,11 @@ v3dv_EnumeratePhysicalDeviceQueueFamilyPerformanceQueryCountersKHR(
|
|||
&out_desc, desc) {
|
||||
desc->flags = 0;
|
||||
snprintf(desc->name, sizeof(desc->name), "%s",
|
||||
v3dv_counters[i][1]);
|
||||
v3d_performance_counters[i][V3D_PERFCNT_NAME]);
|
||||
snprintf(desc->category, sizeof(desc->category), "%s",
|
||||
v3dv_counters[i][0]);
|
||||
v3d_performance_counters[i][V3D_PERFCNT_CATEGORY]);
|
||||
snprintf(desc->description, sizeof(desc->description), "%s",
|
||||
v3dv_counters[i][2]);
|
||||
v3d_performance_counters[i][V3D_PERFCNT_DESCRIPTION]);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -29,6 +29,8 @@
|
|||
|
||||
#include "v3d_query.h"
|
||||
|
||||
#include "common/v3d_performance_counters.h"
|
||||
|
||||
struct v3d_query_perfcnt
|
||||
{
|
||||
struct v3d_query base;
|
||||
|
|
@ -37,96 +39,6 @@ struct v3d_query_perfcnt
|
|||
struct v3d_perfmon_state *perfmon;
|
||||
};
|
||||
|
||||
static const char *v3d_counter_names[] = {
|
||||
"FEP-valid-primitives-no-rendered-pixels",
|
||||
"FEP-valid-primitives-rendered-pixels",
|
||||
"FEP-clipped-quads",
|
||||
"FEP-valid-quads",
|
||||
"TLB-quads-not-passing-stencil-test",
|
||||
"TLB-quads-not-passing-z-and-stencil-test",
|
||||
"TLB-quads-passing-z-and-stencil-test",
|
||||
"TLB-quads-with-zero-coverage",
|
||||
"TLB-quads-with-non-zero-coverage",
|
||||
"TLB-quads-written-to-color-buffer",
|
||||
"PTB-primitives-discarded-outside-viewport",
|
||||
"PTB-primitives-need-clipping",
|
||||
"PTB-primitives-discared-reversed",
|
||||
"QPU-total-idle-clk-cycles",
|
||||
"QPU-total-active-clk-cycles-vertex-coord-shading",
|
||||
"QPU-total-active-clk-cycles-fragment-shading",
|
||||
"QPU-total-clk-cycles-executing-valid-instr",
|
||||
"QPU-total-clk-cycles-waiting-TMU",
|
||||
"QPU-total-clk-cycles-waiting-scoreboard",
|
||||
"QPU-total-clk-cycles-waiting-varyings",
|
||||
"QPU-total-instr-cache-hit",
|
||||
"QPU-total-instr-cache-miss",
|
||||
"QPU-total-uniform-cache-hit",
|
||||
"QPU-total-uniform-cache-miss",
|
||||
"TMU-total-text-quads-access",
|
||||
"TMU-total-text-cache-miss",
|
||||
"VPM-total-clk-cycles-VDW-stalled",
|
||||
"VPM-total-clk-cycles-VCD-stalled",
|
||||
"CLE-bin-thread-active-cycles",
|
||||
"CLE-render-thread-active-cycles",
|
||||
"L2T-total-cache-hit",
|
||||
"L2T-total-cache-miss",
|
||||
"cycle-count",
|
||||
"QPU-total-clk-cycles-waiting-vertex-coord-shading",
|
||||
"QPU-total-clk-cycles-waiting-fragment-shading",
|
||||
"PTB-primitives-binned",
|
||||
"AXI-writes-seen-watch-0",
|
||||
"AXI-reads-seen-watch-0",
|
||||
"AXI-writes-stalled-seen-watch-0",
|
||||
"AXI-reads-stalled-seen-watch-0",
|
||||
"AXI-write-bytes-seen-watch-0",
|
||||
"AXI-read-bytes-seen-watch-0",
|
||||
"AXI-writes-seen-watch-1",
|
||||
"AXI-reads-seen-watch-1",
|
||||
"AXI-writes-stalled-seen-watch-1",
|
||||
"AXI-reads-stalled-seen-watch-1",
|
||||
"AXI-write-bytes-seen-watch-1",
|
||||
"AXI-read-bytes-seen-watch-1",
|
||||
"TLB-partial-quads-written-to-color-buffer",
|
||||
"TMU-total-config-access",
|
||||
"L2T-no-id-stalled",
|
||||
"L2T-command-queue-stalled",
|
||||
"L2T-TMU-writes",
|
||||
"TMU-active-cycles",
|
||||
"TMU-stalled-cycles",
|
||||
"CLE-thread-active-cycles",
|
||||
"L2T-TMU-reads",
|
||||
"L2T-CLE-reads",
|
||||
"L2T-VCD-reads",
|
||||
"L2T-TMU-config-reads",
|
||||
"L2T-SLC0-reads",
|
||||
"L2T-SLC1-reads",
|
||||
"L2T-SLC2-reads",
|
||||
"L2T-TMU-write-miss",
|
||||
"L2T-TMU-read-miss",
|
||||
"L2T-CLE-read-miss",
|
||||
"L2T-VCD-read-miss",
|
||||
"L2T-TMU-config-read-miss",
|
||||
"L2T-SLC0-read-miss",
|
||||
"L2T-SLC1-read-miss",
|
||||
"L2T-SLC2-read-miss",
|
||||
"core-memory-writes",
|
||||
"L2T-memory-writes",
|
||||
"PTB-memory-writes",
|
||||
"TLB-memory-writes",
|
||||
"core-memory-reads",
|
||||
"L2T-memory-reads",
|
||||
"PTB-memory-reads",
|
||||
"PSE-memory-reads",
|
||||
"TLB-memory-reads",
|
||||
"GMP-memory-reads",
|
||||
"PTB-memory-words-writes",
|
||||
"TLB-memory-words-writes",
|
||||
"PSE-memory-words-reads",
|
||||
"TLB-memory-words-reads",
|
||||
"TMU-MRU-hits",
|
||||
"compute-active-cycles",
|
||||
};
|
||||
|
||||
static void
|
||||
kperfmon_destroy(struct v3d_context *v3d, struct v3d_perfmon_state *perfmon)
|
||||
{
|
||||
|
|
@ -154,7 +66,7 @@ v3d_get_driver_query_group_info_perfcnt(struct v3d_screen *screen, unsigned inde
|
|||
|
||||
info->name = "V3D counters";
|
||||
info->max_active_queries = DRM_V3D_MAX_PERF_COUNTERS;
|
||||
info->num_queries = ARRAY_SIZE(v3d_counter_names);
|
||||
info->num_queries = ARRAY_SIZE(v3d_performance_counters);
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
|
@ -167,13 +79,13 @@ v3d_get_driver_query_info_perfcnt(struct v3d_screen *screen, unsigned index,
|
|||
return 0;
|
||||
|
||||
if (!info)
|
||||
return ARRAY_SIZE(v3d_counter_names);
|
||||
return ARRAY_SIZE(v3d_performance_counters);
|
||||
|
||||
if (index >= ARRAY_SIZE(v3d_counter_names))
|
||||
if (index >= ARRAY_SIZE(v3d_performance_counters))
|
||||
return 0;
|
||||
|
||||
info->group_id = 0;
|
||||
info->name = v3d_counter_names[index];
|
||||
info->name = v3d_performance_counters[index][V3D_PERFCNT_NAME];
|
||||
info->query_type = PIPE_QUERY_DRIVER_SPECIFIC + index;
|
||||
info->result_type = PIPE_DRIVER_QUERY_RESULT_TYPE_CUMULATIVE;
|
||||
info->type = PIPE_DRIVER_QUERY_TYPE_UINT64;
|
||||
|
|
@ -322,7 +234,7 @@ v3d_create_batch_query_perfcnt(struct v3d_context *v3d, unsigned num_queries,
|
|||
for (i = 0; i < num_queries; i++) {
|
||||
if (query_types[i] < PIPE_QUERY_DRIVER_SPECIFIC ||
|
||||
query_types[i] >= PIPE_QUERY_DRIVER_SPECIFIC +
|
||||
ARRAY_SIZE(v3d_counter_names)) {
|
||||
ARRAY_SIZE(v3d_performance_counters)) {
|
||||
fprintf(stderr, "Invalid query type\n");
|
||||
return NULL;
|
||||
}
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue