diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_blitter.cc b/src/gallium/drivers/freedreno/a6xx/fd6_blitter.cc index b79aa4f4f10..35fc84c199c 100644 --- a/src/gallium/drivers/freedreno/a6xx/fd6_blitter.cc +++ b/src/gallium/drivers/freedreno/a6xx/fd6_blitter.cc @@ -267,8 +267,7 @@ emit_setup(struct fd_context *ctx, fd_cs &cs) FD6_FLUSH_CCU_DEPTH | FD6_INVALIDATE_CCU_DEPTH); - fd_pkt7(cs, CP_SET_MARKER, 1) - .add(A6XX_CP_SET_MARKER_0_MODE(RM6_BLIT2DSCALE)); + fd6_set_render_mode(cs, {RM6_BLIT2DSCALE}); /* normal BLIT_OP_SCALE operation needs bypass RB_CCU_CNTL */ fd6_emit_gmem_cache_cntl(cs, ctx->screen, false); @@ -505,8 +504,7 @@ fd6_clear_ubwc(struct fd_batch *batch, struct fd_resource *rsc) assert_dt { fd_cs cs(fd_batch_get_prologue(batch)); - fd_pkt7(cs, CP_SET_MARKER, 1) - .add(A6XX_CP_SET_MARKER_0_MODE(RM6_BLIT2DSCALE)); + fd6_set_render_mode(cs, {RM6_BLIT2DSCALE}); clear_ubwc_setup(cs); diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_compute.cc b/src/gallium/drivers/freedreno/a6xx/fd6_compute.cc index c77d3058136..2d15d871ad8 100644 --- a/src/gallium/drivers/freedreno/a6xx/fd6_compute.cc +++ b/src/gallium/drivers/freedreno/a6xx/fd6_compute.cc @@ -174,8 +174,7 @@ fd6_launch_grid(struct fd_context *ctx, const struct pipe_grid_info *info) in_dt fd_cs cs(ctx->batch->draw); - fd_pkt7(cs, CP_SET_MARKER, 1) - .add(A6XX_CP_SET_MARKER_0_MODE(RM6_COMPUTE)); + fd6_set_render_mode(cs, {RM6_COMPUTE}); trace_start_compute(&ctx->batch->trace, cs, !!info->indirect, info->work_dim, info->block[0], info->block[1], info->block[2], diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_emit.h b/src/gallium/drivers/freedreno/a6xx/fd6_emit.h index 80b039976f1..5c055766041 100644 --- a/src/gallium/drivers/freedreno/a6xx/fd6_emit.h +++ b/src/gallium/drivers/freedreno/a6xx/fd6_emit.h @@ -302,6 +302,19 @@ fd6_set_rb_dbg_eco_mode(struct fd_context *ctx, fd_cs &cs, bool blit) .add(A6XX_RB_DBG_ECO_CNTL(.dword = dword)); } +struct fd6_set_render_mode { + enum a6xx_marker mode; + bool uses_gmem; +}; + +template +static inline void +fd6_set_render_mode(fd_cs &cs, struct fd6_set_render_mode args) +{ + fd_pkt7(cs, CP_SET_MARKER, 1) + .add(A6XX_CP_SET_MARKER_0(.mode = args.mode, .uses_gmem = args.uses_gmem)); +} + static inline bool fd6_geom_stage(mesa_shader_stage type) { diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_gmem.cc b/src/gallium/drivers/freedreno/a6xx/fd6_gmem.cc index 1c3110e1e37..edd50fb090a 100644 --- a/src/gallium/drivers/freedreno/a6xx/fd6_gmem.cc +++ b/src/gallium/drivers/freedreno/a6xx/fd6_gmem.cc @@ -316,12 +316,8 @@ emit_lrz_clears(struct fd_batch *batch) /* prep before first clear: */ if (count == 0) { fd6_emit_gmem_cache_cntl(cs, ctx->screen, false); - - fd_pkt7(cs, CP_SET_MARKER, 1) - .add(A6XX_CP_SET_MARKER_0_MODE(RM6_BLIT2DSCALE)); - + fd6_set_render_mode(cs, {RM6_BLIT2DSCALE}); fd6_emit_flushes(ctx, cs, FD6_FLUSH_CACHE); - fd6_set_rb_dbg_eco_mode(ctx, cs, true); } @@ -948,8 +944,7 @@ emit_binning_pass(fd_cs &cs, struct fd_batch *batch) assert_dt set_scissor(cs, 0, 0, gmem->width - 1, gmem->height - 1); - fd_pkt7(cs, CP_SET_MARKER, 1) - .add(A6XX_CP_SET_MARKER_0_MODE(RM6_BIN_VISIBILITY)); + fd6_set_render_mode(cs, {RM6_BIN_VISIBILITY}); fd_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1) .add(0x1); @@ -1008,8 +1003,7 @@ emit_binning_pass(fd_cs &cs, struct fd_batch *batch) assert_dt .add(0x0); if (CHIP >= A7XX) { - fd_pkt7(cs, CP_SET_MARKER, 1) - .add(A6XX_CP_SET_MARKER_0_MODE(RM7_BIN_VISIBILITY_END)); + fd6_set_render_mode(cs, {RM7_BIN_VISIBILITY_END}); } } @@ -1269,9 +1263,7 @@ fd6_emit_tile_prep(struct fd_batch *batch, const struct fd_tile *tile) struct fd6_context *fd6_ctx = fd6_context(ctx); fd_cs cs(batch->gmem); - fd_pkt7(cs, CP_SET_MARKER, 1) - .add(A6XX_CP_SET_MARKER_0_MODE(RM6_BIN_RENDER_START) | - A6XX_CP_SET_MARKER_0_USES_GMEM); + fd6_set_render_mode(cs, {.mode = RM6_BIN_RENDER_START, .uses_gmem = true}); uint32_t x1 = tile->xoff; uint32_t y1 = tile->yoff; @@ -1905,8 +1897,7 @@ fd6_emit_tile_gmem2mem(struct fd_batch *batch, const struct fd_tile *tile) fd6_emit_ib(cs, batch->epilogue); if (use_hw_binning(batch)) { - fd_pkt7(cs, CP_SET_MARKER, 1) - .add(A6XX_CP_SET_MARKER_0(.mode = RM6_BIN_END_OF_DRAWS, .uses_gmem = true)); + fd6_set_render_mode(cs, {.mode = RM6_BIN_END_OF_DRAWS, .uses_gmem = true}); } fd_pkt7(cs, CP_SET_DRAW_STATE, 3) @@ -1916,8 +1907,7 @@ fd6_emit_tile_gmem2mem(struct fd_batch *batch, const struct fd_tile *tile) fd_pkt7(cs, CP_SKIP_IB2_ENABLE_LOCAL, 1) .add(0x0); - fd_pkt7(cs, CP_SET_MARKER, 1) - .add(A6XX_CP_SET_MARKER_0(.mode = RM6_BIN_RESOLVE, .uses_gmem = true)); + fd6_set_render_mode(cs, {.mode = RM6_BIN_RESOLVE, .uses_gmem = true}); if (batch->tile_store) { trace_start_tile_stores(&batch->trace, cs, batch->resolve); @@ -1925,8 +1915,7 @@ fd6_emit_tile_gmem2mem(struct fd_batch *batch, const struct fd_tile *tile) trace_end_tile_stores(&batch->trace, cs); } - fd_pkt7(cs, CP_SET_MARKER, 1) - .add(A6XX_CP_SET_MARKER_0(.mode = RM6_BIN_RENDER_END)); + fd6_set_render_mode(cs, {.mode = RM6_BIN_RENDER_END}); } template @@ -1966,8 +1955,7 @@ emit_sysmem_clears(fd_cs &cs, struct fd_batch *batch, struct fd_batch_subpass *s trace_start_clears(&batch->trace, cs, buffers); - fd_pkt7(cs, CP_SET_MARKER, 1) - .add(A6XX_CP_SET_MARKER_0_MODE(RM6_BLIT2DSCALE)); + fd6_set_render_mode(cs, {RM6_BLIT2DSCALE}); if (buffers & PIPE_CLEAR_COLOR) { for (int i = 0; i < pfb->nr_cbufs; i++) { @@ -2041,8 +2029,7 @@ fd6_emit_sysmem_prep(struct fd_batch *batch) assert_dt if (batch->nondraw) return; - fd_pkt7(cs, CP_SET_MARKER, 1) - .add(A6XX_CP_SET_MARKER_0_MODE(RM6_DIRECT_RENDER)); + fd6_set_render_mode(cs, {RM6_DIRECT_RENDER}); struct pipe_framebuffer_state *pfb = &batch->framebuffer; @@ -2087,8 +2074,7 @@ fd6_emit_sysmem_prep(struct fd_batch *batch) assert_dt crb.add(VPC_SO_OVERRIDE(CHIP, false)); } - fd_pkt7(cs, CP_SET_MARKER, 1) - .add(A6XX_CP_SET_MARKER_0_MODE(RM6_DIRECT_RENDER)); + fd6_set_render_mode(cs, {RM6_DIRECT_RENDER}); fd_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1) .add(0x0); @@ -2135,6 +2121,7 @@ fd6_emit_sysmem(struct fd_batch *batch) fd6_emit_flushes(batch->ctx, cs, flushes); emit_sysmem_clears(cs, batch, subpass); + fd6_set_render_mode(cs, {RM6_DIRECT_RENDER}); } struct pipe_framebuffer_state *pfb = &batch->framebuffer;