From bafa1120ce8b9edeee7fdd5445adf495b3766c9f Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Tapani=20P=C3=A4lli?= <tapani.palli@intel.com>
Date: Fri, 27 Mar 2026 13:47:44 +0200
Subject: [PATCH] genxml/mi: add additional bit to FF_MODE and autostrip helper
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This provides bit and common code to control autostrip state.

Requirement for this is coming from Wa_14026781792. We are writing
register for Wa_14024997852 and since this register is nonmaskable
the bit needs to be written always. Helper takes care to touch only
required bits.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40344>
---
 src/intel/common/mi_builder.h | 40 +++++++++++++++++++++++++++++++++++
 src/intel/genxml/xe2.xml      |  1 +
 2 files changed, 41 insertions(+)

diff --git a/src/intel/common/mi_builder.h b/src/intel/common/mi_builder.h
index b7c6fd81f48..41701d71ce8 100644
--- a/src/intel/common/mi_builder.h
+++ b/src/intel/common/mi_builder.h
@@ -1694,4 +1694,44 @@ mi_goto_target_init_and_place(struct mi_builder *b)
 
 #endif /* GFX_VER >= 9 */
 
+/* Common code for drivers to set autostrip state. */
+#if INTEL_WA_14024997852_GFX_VER
+static inline void
+mi_set_autostrip_state(struct mi_builder *b, bool enable)
+{
+   struct mi_value ff_mode_reg = mi_reg32(GENX(FF_MODE_num));
+
+   uint32_t dword;
+   struct GENX(FF_MODE) ff_mode = {
+      .MeshShaderAutostripDisable = true,
+      .MeshShaderPartialAutostripDisable = true,
+      .TEAutostripDisable = true,
+   };
+   GENX(FF_MODE_pack)(NULL, &dword, &ff_mode);
+
+   /* This bit we want to always enable with Wa_14026781792. */
+   uint32_t bugfix;
+   struct GENX(FF_MODE) ff_mode_bugfix = {
+#if INTEL_NEEDS_WA_14026781792
+     .TEPatchcontrolbugfix = true,
+#endif
+   };
+   GENX(FF_MODE_pack)(NULL, &bugfix, &ff_mode_bugfix);
+
+   if (!enable) {
+      /* Enable flags. */
+      mi_store(b, ff_mode_reg,
+               mi_ior(b,
+                      mi_imm(bugfix),
+                      mi_ior(b, ff_mode_reg, mi_imm(dword))));
+   } else {
+      /* Disable flags. */
+      mi_store(b, ff_mode_reg,
+               mi_ior(b,
+                      mi_imm(bugfix),
+                      mi_iand(b, ff_mode_reg, mi_imm(~dword))));
+   }
+}
+#endif
+
 #endif /* MI_BUILDER_H */
diff --git a/src/intel/genxml/xe2.xml b/src/intel/genxml/xe2.xml
index 6fe36a5b6bd..8b12e296671 100644
--- a/src/intel/genxml/xe2.xml
+++ b/src/intel/genxml/xe2.xml
@@ -1953,6 +1953,7 @@
     <field name="Disable Preemption and High Priority Pausing due to 3DPRIMITIVE Command Mask" dword="0" bits="26:26" type="bool" />
   </register>
   <register name="FF_MODE" length="1" num="0x6210">
+    <field name="TE Patch control bug fix" dword="0" bits="4:4" type="bool" />
     <field name="Mesh Shader Autostrip Disable" dword="0" bits="15:15" type="bool" />
     <field name="Mesh Shader Partial Autostrip Disable" dword="0" bits="16:16" type="bool" />
     <field name="TE Autostrip Disable" dword="0" bits="31:31" type="bool" />