diff --git a/docs/doxygen-wrapper.py b/docs/doxygen-wrapper.py
index e3eb794f9b5..879bd67d89d 100755
--- a/docs/doxygen-wrapper.py
+++ b/docs/doxygen-wrapper.py
@@ -58,6 +58,7 @@ EXPAND_ONLY_PREDEF = YES
 
 # Defines required to keep doxygen from tripping on our attribute macros
 PREDEFINED  = PACKED=
+PREDEFINED += ENUM_PACKED=
 PREDEFINED += ATTRIBUTE_CONST=
 PREDEFINED += MUST_CHECK=
 """)
diff --git a/src/compiler/glsl/ir_uniform.h b/src/compiler/glsl/ir_uniform.h
index 57f77fd3d1b..f44b8e3f4f2 100644
--- a/src/compiler/glsl/ir_uniform.h
+++ b/src/compiler/glsl/ir_uniform.h
@@ -41,7 +41,7 @@
 extern "C" {
 #endif
 
-enum PACKED gl_uniform_driver_format {
+enum ENUM_PACKED gl_uniform_driver_format {
    uniform_native = 0,          /**< Store data in the native format. */
    uniform_int_float,           /**< Store integer data as floats. */
 };
diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h
index 70bfafd0949..56f4618f7ff 100644
--- a/src/compiler/nir/nir.h
+++ b/src/compiler/nir/nir.h
@@ -902,7 +902,7 @@ typedef struct nir_register {
 #define nir_foreach_register_safe(reg, reg_list) \
    foreach_list_typed_safe(nir_register, reg, node, reg_list)
 
-typedef enum PACKED {
+typedef enum ENUM_PACKED {
    nir_instr_type_alu,
    nir_instr_type_deref,
    nir_instr_type_call,
@@ -1265,7 +1265,7 @@ typedef struct {
  * The values in this enum are carefully chosen so that the sized type is
  * just the unsized type OR the number of bits.
  */
-typedef enum PACKED {
+typedef enum ENUM_PACKED {
    nir_type_invalid = 0, /* Not a valid type */
    nir_type_int =       2,
    nir_type_uint =      4,
@@ -5300,7 +5300,7 @@ bool
 nir_lower_sysvals_to_varyings(nir_shader *shader,
                               const struct nir_lower_sysvals_to_varyings_options *options);
 
-enum PACKED nir_lower_tex_packing {
+enum ENUM_PACKED nir_lower_tex_packing {
    /** No packing */
    nir_lower_tex_packing_none = 0,
    /**
diff --git a/src/compiler/nir/nir_range_analysis.h b/src/compiler/nir/nir_range_analysis.h
index 6e842d370f3..dfb8f9419a3 100644
--- a/src/compiler/nir/nir_range_analysis.h
+++ b/src/compiler/nir/nir_range_analysis.h
@@ -25,7 +25,7 @@
 
 #include "nir.h"
 
-enum PACKED ssa_ranges {
+enum ENUM_PACKED ssa_ranges {
    unknown = 0,
    lt_zero,
    le_zero,
diff --git a/src/compiler/nir/nir_search.h b/src/compiler/nir/nir_search.h
index 02e58dcba81..72a5a35c00d 100644
--- a/src/compiler/nir/nir_search.h
+++ b/src/compiler/nir/nir_search.h
@@ -32,7 +32,7 @@
 
 struct nir_builder;
 
-typedef enum PACKED {
+typedef enum ENUM_PACKED {
    nir_search_value_expression,
    nir_search_value_variable,
    nir_search_value_constant,
diff --git a/src/compiler/shader_enums.h b/src/compiler/shader_enums.h
index e88cffd3b2b..e591bd55997 100644
--- a/src/compiler/shader_enums.h
+++ b/src/compiler/shader_enums.h
@@ -1157,7 +1157,7 @@ enum tess_primitive_mode
 /**
  * Mesa primitive types for both GL and Vulkan:
  */
-enum PACKED mesa_prim
+enum ENUM_PACKED mesa_prim
 {
    MESA_PRIM_POINTS,
    MESA_PRIM_LINES,
@@ -1318,7 +1318,7 @@ enum cl_sampler_filter_mode {
 #define MAT_BIT_BACK_INDEXES          (1<<MAT_ATTRIB_BACK_INDEXES)
 
 /** An enum representing what kind of input gl_SubgroupSize is. */
-enum PACKED gl_subgroup_size
+enum ENUM_PACKED gl_subgroup_size
 {
    /** Actual subgroup size, whatever that happens to be */
    SUBGROUP_SIZE_VARYING = 0,
diff --git a/src/intel/compiler/brw_eu_defines.h b/src/intel/compiler/brw_eu_defines.h
index 1f75ac7405a..4b13f4816d8 100644
--- a/src/intel/compiler/brw_eu_defines.h
+++ b/src/intel/compiler/brw_eu_defines.h
@@ -96,7 +96,7 @@ enum brw_compression {
 #define GFX6_COMPRESSION_1H		0
 #define GFX6_COMPRESSION_2H		2
 
-enum PACKED brw_conditional_mod {
+enum ENUM_PACKED brw_conditional_mod {
    BRW_CONDITIONAL_NONE = 0,
    BRW_CONDITIONAL_Z    = 1,
    BRW_CONDITIONAL_NZ   = 2,
@@ -119,7 +119,7 @@ enum PACKED brw_conditional_mod {
 #define BRW_DEPENDENCY_NOTCHECKED     2
 #define BRW_DEPENDENCY_DISABLE        3
 
-enum PACKED brw_execution_size {
+enum ENUM_PACKED brw_execution_size {
    BRW_EXECUTE_1  = 0,
    BRW_EXECUTE_2  = 1,
    BRW_EXECUTE_4  = 2,
@@ -128,21 +128,21 @@ enum PACKED brw_execution_size {
    BRW_EXECUTE_32 = 5,
 };
 
-enum PACKED brw_horizontal_stride {
+enum ENUM_PACKED brw_horizontal_stride {
    BRW_HORIZONTAL_STRIDE_0 = 0,
    BRW_HORIZONTAL_STRIDE_1 = 1,
    BRW_HORIZONTAL_STRIDE_2 = 2,
    BRW_HORIZONTAL_STRIDE_4 = 3,
 };
 
-enum PACKED gfx10_align1_3src_src_horizontal_stride {
+enum ENUM_PACKED gfx10_align1_3src_src_horizontal_stride {
    BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_0 = 0,
    BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_1 = 1,
    BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_2 = 2,
    BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_4 = 3,
 };
 
-enum PACKED gfx10_align1_3src_dst_horizontal_stride {
+enum ENUM_PACKED gfx10_align1_3src_dst_horizontal_stride {
    BRW_ALIGN1_3SRC_DST_HORIZONTAL_STRIDE_1 = 0,
    BRW_ALIGN1_3SRC_DST_HORIZONTAL_STRIDE_2 = 1,
 };
@@ -997,7 +997,7 @@ operator|(brw_urb_write_flags x, brw_urb_write_flags y)
 }
 #endif
 
-enum PACKED brw_predicate {
+enum ENUM_PACKED brw_predicate {
    BRW_PREDICATE_NONE                =  0,
    BRW_PREDICATE_NORMAL              =  1,
    BRW_PREDICATE_ALIGN1_ANYV         =  2,
@@ -1020,7 +1020,7 @@ enum PACKED brw_predicate {
    BRW_PREDICATE_ALIGN16_ALL4H       =  7,
 };
 
-enum PACKED brw_reg_file {
+enum ENUM_PACKED brw_reg_file {
    BRW_ARCHITECTURE_REGISTER_FILE = 0,
    BRW_GENERAL_REGISTER_FILE      = 1,
    BRW_MESSAGE_REGISTER_FILE      = 2,
@@ -1038,7 +1038,7 @@ enum PACKED brw_reg_file {
    BAD_FILE,
 };
 
-enum PACKED gfx10_align1_3src_reg_file {
+enum ENUM_PACKED gfx10_align1_3src_reg_file {
    BRW_ALIGN1_3SRC_GENERAL_REGISTER_FILE = 0,
    BRW_ALIGN1_3SRC_IMMEDIATE_VALUE       = 1, /* src0, src2 */
    BRW_ALIGN1_3SRC_ACCUMULATOR           = 1, /* dest, src1 */
@@ -1049,7 +1049,7 @@ enum PACKED gfx10_align1_3src_reg_file {
  * on float or integer types. The register arguments have fields that offer
  * more fine control their respective types.
  */
-enum PACKED gfx10_align1_3src_exec_type {
+enum ENUM_PACKED gfx10_align1_3src_exec_type {
    BRW_ALIGN1_3SRC_EXEC_TYPE_INT   = 0,
    BRW_ALIGN1_3SRC_EXEC_TYPE_FLOAT = 1,
 };
@@ -1081,7 +1081,7 @@ enum PACKED gfx10_align1_3src_exec_type {
 #define BRW_THREAD_ATOMIC     1
 #define BRW_THREAD_SWITCH     2
 
-enum PACKED brw_vertical_stride {
+enum ENUM_PACKED brw_vertical_stride {
    BRW_VERTICAL_STRIDE_0               = 0,
    BRW_VERTICAL_STRIDE_1               = 1,
    BRW_VERTICAL_STRIDE_2               = 2,
@@ -1092,7 +1092,7 @@ enum PACKED brw_vertical_stride {
    BRW_VERTICAL_STRIDE_ONE_DIMENSIONAL = 0xF,
 };
 
-enum PACKED gfx10_align1_3src_vertical_stride {
+enum ENUM_PACKED gfx10_align1_3src_vertical_stride {
    BRW_ALIGN1_3SRC_VERTICAL_STRIDE_0 = 0,
    BRW_ALIGN1_3SRC_VERTICAL_STRIDE_1 = 1,
    BRW_ALIGN1_3SRC_VERTICAL_STRIDE_2 = 1,
@@ -1100,7 +1100,7 @@ enum PACKED gfx10_align1_3src_vertical_stride {
    BRW_ALIGN1_3SRC_VERTICAL_STRIDE_8 = 3,
 };
 
-enum PACKED brw_width {
+enum ENUM_PACKED brw_width {
    BRW_WIDTH_1  = 0,
    BRW_WIDTH_2  = 1,
    BRW_WIDTH_4  = 2,
@@ -1727,7 +1727,7 @@ enum brw_message_target {
 #define BRW_CR0_RND_MODE_MASK     0x30
 #define BRW_CR0_RND_MODE_SHIFT    4
 
-enum PACKED brw_rnd_mode {
+enum ENUM_PACKED brw_rnd_mode {
    BRW_RND_MODE_RTNE = 0,  /* Round to Nearest or Even */
    BRW_RND_MODE_RU = 1,    /* Round Up, toward +inf */
    BRW_RND_MODE_RD = 2,    /* Round Down, toward -inf */
@@ -1804,7 +1804,7 @@ enum lsc_opcode {
 /*
  * Specifies the size of the dataport address payload in registers.
  */
-enum PACKED lsc_addr_reg_size {
+enum ENUM_PACKED lsc_addr_reg_size {
    LSC_ADDR_REG_SIZE_1  = 1,
    LSC_ADDR_REG_SIZE_2  = 2,
    LSC_ADDR_REG_SIZE_3  = 3,
@@ -1816,7 +1816,7 @@ enum PACKED lsc_addr_reg_size {
 /*
  * Specifies the size of the address payload item in a dataport message.
  */
-enum PACKED lsc_addr_size {
+enum ENUM_PACKED lsc_addr_size {
   LSC_ADDR_SIZE_A16 = 1,    /* 16-bit address offset */
   LSC_ADDR_SIZE_A32 = 2,    /* 32-bit address offset */
   LSC_ADDR_SIZE_A64 = 3,    /* 64-bit address offset */
@@ -1827,7 +1827,7 @@ enum PACKED lsc_addr_size {
  * address type specifies how the dataport message decodes the Extended
  * Descriptor for the surface attributes and address calculation.
  */
-enum PACKED lsc_addr_surface_type {
+enum ENUM_PACKED lsc_addr_surface_type {
    LSC_ADDR_SURFTYPE_FLAT = 0, /* Flat */
    LSC_ADDR_SURFTYPE_BSS = 1,  /* Bindless surface state */
    LSC_ADDR_SURFTYPE_SS = 2,   /* Surface state */
@@ -1867,7 +1867,7 @@ enum lsc_cache_load {
  * (WT), write-back (WB) and streaming (S). Dataport L3 cache policies are
  * uncached (UC) and cached (WB).
  */
-enum PACKED lsc_cache_store {
+enum ENUM_PACKED lsc_cache_store {
    /* No override. Use the non-pipelined or surface state cache settings for L1
     * and L3.
     */
@@ -1893,7 +1893,7 @@ enum PACKED lsc_cache_store {
  * Specifies which components of the data payload 4-element vector (X,Y,Z,W) is
  * packed into the register payload.
  */
-enum PACKED lsc_cmask {
+enum ENUM_PACKED lsc_cmask {
    LSC_CMASK_X = 0x1,
    LSC_CMASK_Y = 0x2,
    LSC_CMASK_XY = 0x3,
@@ -1914,7 +1914,7 @@ enum PACKED lsc_cmask {
 /*
  * Specifies the size of the data payload item in a dataport message.
  */
-enum PACKED lsc_data_size {
+enum ENUM_PACKED lsc_data_size {
    /* 8-bit scalar data value in memory, packed into a 8-bit data value in
     * register.
     */
@@ -1948,7 +1948,7 @@ enum PACKED lsc_data_size {
 /*
  *  Enum specifies the scope of the fence.
  */
-enum PACKED lsc_fence_scope {
+enum ENUM_PACKED lsc_fence_scope {
    /* Wait until all previous memory transactions from this thread are observed
     * within the local thread-group.
     */
@@ -1985,7 +1985,7 @@ enum PACKED lsc_fence_scope {
  * Specifies the type of cache flush operation to perform after a fence is
  * complete.
  */
-enum PACKED lsc_flush_type {
+enum ENUM_PACKED lsc_flush_type {
    LSC_FLUSH_TYPE_NONE = 0,
    /*
     * For a R/W cache, evict dirty lines (M to I state) and invalidate clean
@@ -2018,7 +2018,7 @@ enum PACKED lsc_flush_type {
 
 };
 
-enum PACKED lsc_backup_fence_routing {
+enum ENUM_PACKED lsc_backup_fence_routing {
    /* Normal routing: UGM fence is routed to UGM pipeline. */
    LSC_NORMAL_ROUTING,
    /* Route UGM fence to LSC unit. */
@@ -2028,7 +2028,7 @@ enum PACKED lsc_backup_fence_routing {
 /*
  * Specifies the size of the vector in a dataport message.
  */
-enum PACKED lsc_vect_size {
+enum ENUM_PACKED lsc_vect_size {
    LSC_VECT_SIZE_V1 = 0,    /* vector length 1 */
    LSC_VECT_SIZE_V2 = 1,    /* vector length 2 */
    LSC_VECT_SIZE_V3 = 2,    /* Vector length 3 */
diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h
index 3a754874f29..f16f63de2c8 100644
--- a/src/intel/isl/isl.h
+++ b/src/intel/isl/isl.h
@@ -415,7 +415,7 @@ enum isl_format {
 /**
  * Numerical base type for channels of isl_format.
  */
-enum PACKED isl_base_type {
+enum ENUM_PACKED isl_base_type {
    /** Data which takes up space but is ignored */
    ISL_VOID,
 
@@ -1140,7 +1140,7 @@ typedef uint8_t isl_channel_mask_t;
 /**
  * @brief A channel select (also known as texture swizzle) value
  */
-enum PACKED isl_channel_select {
+enum ENUM_PACKED isl_channel_select {
    ISL_CHANNEL_SELECT_ZERO = 0,
    ISL_CHANNEL_SELECT_ONE = 1,
    ISL_CHANNEL_SELECT_RED = 4,
diff --git a/src/intel/perf/intel_perf.h b/src/intel/perf/intel_perf.h
index 9c6e6f9c44d..33d1206a667 100644
--- a/src/intel/perf/intel_perf.h
+++ b/src/intel/perf/intel_perf.h
@@ -55,7 +55,7 @@ struct intel_perf_query_info;
 
 #define INTEL_PERF_INVALID_CTX_ID (0xffffffff)
 
-enum PACKED intel_perf_counter_type {
+enum ENUM_PACKED intel_perf_counter_type {
    INTEL_PERF_COUNTER_TYPE_EVENT,
    INTEL_PERF_COUNTER_TYPE_DURATION_NORM,
    INTEL_PERF_COUNTER_TYPE_DURATION_RAW,
@@ -64,7 +64,7 @@ enum PACKED intel_perf_counter_type {
    INTEL_PERF_COUNTER_TYPE_TIMESTAMP,
 };
 
-enum PACKED intel_perf_counter_data_type {
+enum ENUM_PACKED intel_perf_counter_data_type {
    INTEL_PERF_COUNTER_DATA_TYPE_BOOL32,
    INTEL_PERF_COUNTER_DATA_TYPE_UINT32,
    INTEL_PERF_COUNTER_DATA_TYPE_UINT64,
@@ -72,7 +72,7 @@ enum PACKED intel_perf_counter_data_type {
    INTEL_PERF_COUNTER_DATA_TYPE_DOUBLE,
 };
 
-enum PACKED intel_perf_counter_units {
+enum ENUM_PACKED intel_perf_counter_units {
    /* size */
    INTEL_PERF_COUNTER_UNITS_BYTES,
    INTEL_PERF_COUNTER_UNITS_GBPS,
diff --git a/src/mesa/main/menums.h b/src/mesa/main/menums.h
index 51e0ea16703..ff8d310cc2a 100644
--- a/src/mesa/main/menums.h
+++ b/src/mesa/main/menums.h
@@ -82,7 +82,7 @@ _mesa_is_api_gles2(gl_api api)
  *
  *    result_bit = logic_op & (1 << (2 * src_bit + dst_bit))
  */
-enum PACKED gl_logicop_mode {
+enum ENUM_PACKED gl_logicop_mode {
    COLOR_LOGICOP_CLEAR = 0,
    COLOR_LOGICOP_NOR = 1,
    COLOR_LOGICOP_AND_INVERTED = 2,
diff --git a/src/util/macros.h b/src/util/macros.h
index c474d7571d7..bffabfb52a8 100644
--- a/src/util/macros.h
+++ b/src/util/macros.h
@@ -209,8 +209,10 @@ do {                       \
 #  else
 #    define PACKED __attribute__((__packed__))
 #  endif
+#  define ENUM_PACKED __attribute__((packed))
 #else
 #define PACKED
+#define ENUM_PACKED
 #endif
 
 /* Attribute pure is used for functions that have no effects other than their
diff --git a/src/vulkan/runtime/vk_graphics_state.h b/src/vulkan/runtime/vk_graphics_state.h
index 56fb0213b28..09ae1b407bf 100644
--- a/src/vulkan/runtime/vk_graphics_state.h
+++ b/src/vulkan/runtime/vk_graphics_state.h
@@ -219,7 +219,7 @@ struct vk_discard_rectangles_state {
    VkRect2D rectangles[MESA_VK_MAX_DISCARD_RECTANGLES];
 };
 
-enum PACKED vk_mesa_depth_clip_enable {
+enum ENUM_PACKED vk_mesa_depth_clip_enable {
    /** Depth clipping should be disabled */
    VK_MESA_DEPTH_CLIP_ENABLE_FALSE = 0,