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radv: fix emitting RBPLUS state when MRTs are compacted

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The RBPLUS state needs the non-compacted SPI_SHADER_COL_FORMAT value,
otherwise the state is wrongly emitted if there is holes.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7348
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7319
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7365
Fixes: 8fcb4aa0eb ("radv: compact MRTs to save PS export memory space")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18818>
This commit is contained in:
Samuel Pitoiset 2022-09-26 11:44:13 +02:00 • committed by Marge Bot
parent 1dd5d94f65
commit bad75ed3f1
3 changed files with 8 additions and 4 deletions
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2
src/amd/vulkan/radv_cmd_buffer.c
View file

@ -1268,7 +1268,7 @@ radv_emit_rbplus_state(struct radv_cmd_buffer *cmd_buffer)
? !G_028C74_FORCE_DST_ALPHA_1_GFX11(cb->cb_color_attrib)
: !G_028C74_FORCE_DST_ALPHA_1_GFX6(cb->cb_color_attrib);
uint32_t spi_format = (pipeline->col_format >> (i * 4)) & 0xf;
uint32_t spi_format = (pipeline->col_format_non_compacted >> (i * 4)) & 0xf;
uint32_t colormask = (pipeline->cb_target_mask >> (i * 4)) & 0xf;
if (format == V_028C70_COLOR_8 || format == V_028C70_COLOR_16 || format == V_028C70_COLOR_32)

8
src/amd/vulkan/radv_pipeline.c
View file

@ -6189,6 +6189,9 @@ radv_graphics_pipeline_init(struct radv_graphics_pipeline *pipeline, struct radv
if (device->physical_device->rad_info.gfx_level >= GFX10_3)
gfx103_pipeline_init_vrs_state(pipeline, &state);
/* Copy the non-compacted SPI_SHADER_COL_FORMAT which is used to emit RBPLUS state. */
pipeline->col_format_non_compacted = blend.spi_shader_col_format;
struct radv_shader *ps = pipeline->base.shaders[MESA_SHADER_FRAGMENT];
if (!ps->info.ps.has_epilog) {
blend.spi_shader_col_format = radv_compact_spi_shader_col_format(ps, &blend);
@ -6211,8 +6214,10 @@ radv_graphics_pipeline_init(struct radv_graphics_pipeline *pipeline, struct radv
*/
if ((device->physical_device->rad_info.gfx_level <= GFX9 || ps->info.ps.can_discard) &&
!blend.spi_shader_col_format) {
if (!ps->info.ps.writes_z && !ps->info.ps.writes_stencil && !ps->info.ps.writes_sample_mask)
if (!ps->info.ps.writes_z && !ps->info.ps.writes_stencil && !ps->info.ps.writes_sample_mask) {
blend.spi_shader_col_format = V_028714_SPI_SHADER_32_R;
pipeline->col_format_non_compacted = V_028714_SPI_SHADER_32_R;
}
}
if (!ps->info.ps.has_epilog) {
@ -6224,7 +6229,6 @@ radv_graphics_pipeline_init(struct radv_graphics_pipeline *pipeline, struct radv
blend.cb_shader_mask &= ps->info.ps.colors_written;
}
pipeline->col_format = blend.spi_shader_col_format;
pipeline->cb_target_mask = blend.cb_target_mask;
if (radv_pipeline_has_stage(pipeline, MESA_SHADER_GEOMETRY) && !radv_pipeline_has_ngg(pipeline)) {

2
src/amd/vulkan/radv_private.h
View file

@ -2033,7 +2033,7 @@ struct radv_graphics_pipeline {
struct radv_userdata_info *last_vgt_api_stage_locs;
/* Used for rbplus */
uint32_t col_format;
uint32_t col_format_non_compacted;
uint32_t cb_target_mask;
bool disable_out_of_order_rast_for_occlusion;