fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-05-05 13:58:04 +02:00
Code Issues Projects Releases Packages Wiki Activity Actions 2

pan/mdg: Emulate 8-bit with the 16-bit pipe

Browse source 
We don't care to support i8vec16, we just need a bit of 8-bit support to
implement format packing/unpacking in blend shaders. We're already doing
this by using the 16-bit pipe, we just need to commit to it all the way
-- reporting the correct sizes in max_bitsize_for_alu so the mask
packing logic works as intended -- and dropping the imov-specific hack
that was introduced to workaround a similar class of bugs.

With the previous patch, fixes:

   dEQP-GLES31.functional.draw_buffers_indexed.random.max_required_draw_buffers.1

Fixes: 39e4b7279d ("pan/midg: Fix swizzling on 8-bit sources")
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19763>
(cherry picked from commit 976405907e)
This commit is contained in:
Alyssa Rosenzweig 2022-10-27 21:28:34 -04:00 • committed by Eric Engestrom
parent 88cb57c8eb
commit ba9ee546d5
5 changed files with 9 additions and 20 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
.pick_status.json
View file

@ -5872,7 +5872,7 @@
"description": "pan/mdg: Emulate 8-bit with the 16-bit pipe",
"nominated": true,
"nomination_type": 1,
"resolution": 0,
"resolution": 1,
"main_sha": null,
"because_sha": "39e4b7279dcdcef91a0e829a1938b2816aa4ce75"
},

4
src/panfrost/ci/panfrost-t860-fails.txt
View file

@ -4,11 +4,9 @@ dEQP-GLES3.functional.draw_buffers_indexed.random.max_implementation_draw_buffer
dEQP-GLES3.functional.draw_buffers_indexed.random.max_implementation_draw_buffers.3,Fail
dEQP-GLES3.functional.draw_buffers_indexed.random.max_implementation_draw_buffers.4,Fail
dEQP-GLES3.functional.draw_buffers_indexed.random.max_implementation_draw_buffers.5,Fail
dEQP-GLES3.functional.draw_buffers_indexed.random.max_implementation_draw_buffers.7,Fail
dEQP-GLES3.functional.draw_buffers_indexed.random.max_implementation_draw_buffers.8,Fail
dEQP-GLES3.functional.draw_buffers_indexed.random.max_implementation_draw_buffers.9,Fail
dEQP-GLES3.functional.draw_buffers_indexed.random.max_implementation_draw_buffers.10,Fail
dEQP-GLES3.functional.draw_buffers_indexed.random.max_implementation_draw_buffers.11,Fail
dEQP-GLES3.functional.draw_buffers_indexed.random.max_implementation_draw_buffers.12,Fail
dEQP-GLES3.functional.draw_buffers_indexed.random.max_implementation_draw_buffers.13,Fail
dEQP-GLES3.functional.draw_buffers_indexed.random.max_implementation_draw_buffers.14,Fail
@ -17,7 +15,6 @@ dEQP-GLES3.functional.draw_buffers_indexed.random.max_implementation_draw_buffer
dEQP-GLES3.functional.draw_buffers_indexed.random.max_implementation_draw_buffers.17,Fail
dEQP-GLES3.functional.draw_buffers_indexed.random.max_implementation_draw_buffers.18,Fail
dEQP-GLES3.functional.draw_buffers_indexed.random.max_implementation_draw_buffers.19,Fail
dEQP-GLES3.functional.draw_buffers_indexed.random.max_required_draw_buffers.1,Fail
dEQP-GLES3.functional.draw_buffers_indexed.random.max_required_draw_buffers.2,Fail
dEQP-GLES3.functional.draw_buffers_indexed.random.max_required_draw_buffers.10,Fail
dEQP-GLES3.functional.draw_buffers_indexed.random.max_required_draw_buffers.11,Fail
@ -25,7 +22,6 @@ dEQP-GLES3.functional.draw_buffers_indexed.random.max_required_draw_buffers.12,F
dEQP-GLES3.functional.draw_buffers_indexed.random.max_required_draw_buffers.15,Fail
dEQP-GLES3.functional.draw_buffers_indexed.random.max_required_draw_buffers.16,Fail
dEQP-GLES3.functional.draw_buffers_indexed.random.max_required_draw_buffers.17,Fail
dEQP-GLES3.functional.draw_buffers_indexed.random.max_required_draw_buffers.18,Fail
dEQP-GLES3.functional.fbo.blit.rect.nearest_consistency_mag,Fail
dEQP-GLES3.functional.fbo.blit.rect.nearest_consistency_mag_reverse_dst_x,Fail
dEQP-GLES3.functional.fbo.blit.rect.nearest_consistency_mag_reverse_dst_y,Fail

3
src/panfrost/midgard/midgard_compile.c
View file

@ -2650,6 +2650,9 @@ max_bitsize_for_alu(midgard_instruction *ins)
unsigned dst_bitsize = nir_alu_type_get_type_size(ins->dest_type);
max_bitsize = MAX2(dst_bitsize, max_bitsize);
/* We emulate 8-bit as 16-bit for simplicity of packing */
max_bitsize = MAX2(max_bitsize, 16);
/* We don't have fp16 LUTs, so we'll want to emit code like:
*
* vlut.fsinr hr0, hr0

6
src/panfrost/midgard/midgard_emit.c
View file

@ -340,12 +340,6 @@ mir_pack_vector_srcs(midgard_instruction *ins, midgard_vector_alu *alu)
unsigned sz = nir_alu_type_get_type_size(ins->src_types[i]);
assert((sz == base_size) || (sz == base_size / 2));
/* Promote 8bit moves to 16bit ones so we can support any swizzles. */
if (sz == 8 && base_size == 8 && ins->op == midgard_alu_op_imov) {
ins->outmod = midgard_outmod_keeplo;
base_size = 16;
}
midgard_src_expand_mode expand_mode = midgard_src_passthrough;
unsigned swizzle = mir_pack_swizzle(ins->mask, ins->swizzle[i],
sz, base_size, channeled,

14
src/panfrost/midgard/mir.c
View file

@ -232,20 +232,16 @@ mir_set_bytemask(midgard_instruction *ins, uint16_t bytemask)
ins->mask = mir_from_bytemask(bytemask, type_size);
}
/* Checks if we should use an upper destination override, rather than the lower
* one in the IR. Returns zero if no, returns the bytes to shift otherwise */
/*
* Checks if we should use an upper destination override, rather than the lower
* one in the IR. If yes, returns the bytes to shift by. If no, returns zero
* for a lower override and negative for no override.
*/
signed
mir_upper_override(midgard_instruction *ins, unsigned inst_size)
{
unsigned type_size = nir_alu_type_get_type_size(ins->dest_type);
/* 8bit imovs are promoted to 16bit ones with .sext on the source and
* .keeplo on the destination to accomodate with non-identity swizzles.
*/
if (ins->op == midgard_alu_op_imov && type_size == 8)
return 0;
/* If the sizes are the same, there's nothing to override */
if (type_size == inst_size)
return -1;