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ir3/postsched: Make sure to schedule inputs before kill
Before, we would prefer to schedule inputs before kills, which works assuming that the live range of the bary_ij system value don't get split and therefore all bary.f are ready at the start of the block. However live range splitting can mess up that assumption and cause a kill to get scheduled before a move that leads to a bary.f. This fixes even e.g. dEQP-GLES2.functional.shaders.discard.basic_always on a3xx before introducing CSE of collect instructions, but even after that it could be a problem theoretically as the register allocator doesn't guarantee that any live ranges aren't split. Reviewed-by: Eric Anholt <eric@anholt.net> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10143>
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1 changed files with 15 additions and 1 deletions
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@ -527,6 +527,13 @@ sched_dag_init(struct ir3_postsched_ctx *ctx)
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struct util_dynarray kills;
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util_dynarray_init(&kills, ctx->mem_ctx);
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/* The last bary.f with the (ei) flag must be scheduled before any kills,
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* or the hw gets angry. Keep track of inputs here so we can add the
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* false dep on the kill instruction.
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*/
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struct util_dynarray inputs;
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util_dynarray_init(&inputs, ctx->mem_ctx);
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/*
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* Normal srcs won't be in SSA at this point, those are dealt with in
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* calculate_forward_deps() and calculate_reverse_deps(). But we still
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@ -553,7 +560,14 @@ sched_dag_init(struct ir3_postsched_ctx *ctx)
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dag_add_edge(&sn->dag, &n->dag, NULL);
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}
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if (is_kill(instr)) {
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if (is_input(instr)) {
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util_dynarray_append(&inputs, struct ir3_instruction *, instr);
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} else if (is_kill(instr)) {
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util_dynarray_foreach(&inputs, struct ir3_instruction *, instrp) {
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struct ir3_instruction *input = *instrp;
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struct ir3_postsched_node *in = input->data;
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dag_add_edge(&in->dag, &n->dag, NULL);
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}
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util_dynarray_append(&kills, struct ir3_instruction *, instr);
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} else if (is_tex(instr) || is_mem(instr)) {
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util_dynarray_foreach(&kills, struct ir3_instruction *, instrp) {
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