From ba209fe493e4977e1d4edbf413dd8d7da2015b9e Mon Sep 17 00:00:00 2001
From: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Date: Thu, 24 Nov 2022 20:40:46 -0500
Subject: [PATCH] agx: Implement formatted loads

These will be generated by the UBO and VBO lowerings. (and eventually by other
lowerings too?)

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19996>
---
 src/asahi/compiler/agx_compile.c          | 24 +++++++++++++++++++++++
 src/asahi/compiler/agx_nir_opt_preamble.c |  2 ++
 2 files changed, 26 insertions(+)

diff --git a/src/asahi/compiler/agx_compile.c b/src/asahi/compiler/agx_compile.c
index 86481ff5f20..ac7509d9d2f 100644
--- a/src/asahi/compiler/agx_compile.c
+++ b/src/asahi/compiler/agx_compile.c
@@ -609,6 +609,25 @@ agx_emit_load_ubo(agx_builder *b, agx_index dst, nir_intrinsic_instr *instr)
    return NULL;
 }
 
+static void
+agx_emit_load(agx_builder *b, agx_index dest, nir_intrinsic_instr *instr)
+{
+   agx_index addr = agx_src_index(&instr->src[0]);
+   agx_index offset = agx_src_index(&instr->src[1]);
+   enum agx_format fmt = agx_format_for_pipe(nir_intrinsic_format(instr));
+   unsigned shift = nir_intrinsic_base(instr);
+
+   /* Zero-extend offset if we're not sign-extending */
+   if (!nir_intrinsic_sign_extend(instr))
+      offset = agx_abs(offset);
+
+   agx_device_load_to(b, dest, addr, offset, fmt,
+                      BITFIELD_MASK(nir_dest_num_components(instr->dest)),
+                      shift, 0);
+   agx_wait(b, 0);
+   agx_emit_cached_split(b, dest, nir_dest_num_components(instr->dest));
+}
+
 /* Preambles write directly to uniform registers, so move from uniform to GPR */
 static agx_instr *
 agx_emit_load_preamble(agx_builder *b, agx_index dst, nir_intrinsic_instr *instr)
@@ -764,6 +783,11 @@ agx_emit_intrinsic(agx_builder *b, nir_intrinsic_instr *instr)
         agx_emit_load_global(b, dst, instr);
         return NULL;
 
+  case nir_intrinsic_load_agx:
+  case nir_intrinsic_load_constant_agx:
+     agx_emit_load(b, dst, instr);
+     return NULL;
+
   case nir_intrinsic_store_output:
      assert(stage == MESA_SHADER_VERTEX);
      return agx_emit_store_vary(b, instr);
diff --git a/src/asahi/compiler/agx_nir_opt_preamble.c b/src/asahi/compiler/agx_nir_opt_preamble.c
index 8e4ae11d206..46829fb21bc 100644
--- a/src/asahi/compiler/agx_nir_opt_preamble.c
+++ b/src/asahi/compiler/agx_nir_opt_preamble.c
@@ -81,7 +81,9 @@ instr_cost(nir_instr *instr, const void *data)
    case nir_instr_type_intrinsic:
       switch (nir_instr_as_intrinsic(instr)->intrinsic) {
       case nir_intrinsic_load_global:
+      case nir_intrinsic_load_agx:
       case nir_intrinsic_load_global_constant:
+      case nir_intrinsic_load_constant_agx:
       case nir_intrinsic_load_ubo:
          return 10.0;
       default: