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iris: Add pre-draw flushing for stream output targets

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When stream output is active, we need to let the cache tracker know
about any SO buffers, which we access via IRIS_DOMAIN_OTHER_WRITE.

In particular, we may have written to those buffers via another
mechanism, such as BLORP buffer copies.  In that case, previous writes
happened via IRIS_DOMAIN_RENDER_WRITE, in which case we'd need to flush
both the render cache and the tile cache to make that data globally-
observable before we begin writing via streamout, which is incoherent
with the earlier mechanism.

Fixes misrendering in Ryujinx.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6085
Fixes: d8cb76211c ("iris: Fix MOCS for buffer copies")
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15275>
(cherry picked from commit 9c8874b9ab)
This commit is contained in:
Kenneth Graunke 2022-03-07 22:01:08 -08:00 • committed by Dylan Baker
parent c1346ca615
commit ba171ded1d
3 changed files with 15 additions and 1 deletions
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2
.pick_status.json
View file

@ -2276,7 +2276,7 @@
"description": "iris: Add pre-draw flushing for stream output targets",
"nominated": true,
"nomination_type": 1,
"resolution": 0,
"resolution": 1,
"because_sha": "d8cb76211c5d264d705dbd3c02b5fc61637d5a56"
},
{

11
src/gallium/drivers/iris/iris_resolve.c
View file

@ -413,6 +413,17 @@ iris_predraw_flush_buffers(struct iris_context *ice,
if (ice->state.stage_dirty & (IRIS_STAGE_DIRTY_BINDINGS_VS << stage))
flush_ssbos(batch, shs);
if (ice->state.streamout_active &&
(ice->state.dirty & IRIS_DIRTY_SO_BUFFERS)) {
for (int i = 0; i < 4; i++) {
struct iris_stream_output_target *tgt = (void *)ice->state.so_target[i];
if (tgt) {
struct iris_bo *bo = iris_resource_bo(tgt->base.buffer);
iris_emit_buffer_barrier_for(batch, bo, IRIS_DOMAIN_OTHER_WRITE);
}
}
}
}
static void

3
src/gallium/drivers/iris/iris_resource.c
View file

@ -2547,6 +2547,9 @@ iris_dirty_for_history(struct iris_context *ice,
if (res->bind_history & PIPE_BIND_VERTEX_BUFFER)
dirty |= IRIS_DIRTY_VERTEX_BUFFER_FLUSHES;
if (ice->state.streamout_active && (res->bind_history & PIPE_BIND_STREAM_OUTPUT))
dirty |= IRIS_DIRTY_SO_BUFFERS;
ice->state.dirty |= dirty;
ice->state.stage_dirty |= stage_dirty;
}