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radeonsi: preserve the scanout flag for shared resources on gfx9 and gfx10

Browse source 
Closes: #2195
Closes: #2294

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
This commit is contained in:
Marek Olšák 2019-12-27 15:53:12 -05:00
parent 1de06e540a
commit ba10fb3f7f
3 changed files with 11 additions and 10 deletions
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2
src/gallium/drivers/radeon/radeon_winsys.h
View file

@ -220,6 +220,8 @@ struct radeon_bo_metadata {
unsigned dcc_offset_256B:24;
unsigned dcc_pitch_max:14; /* (mip chain pitch - 1) for DCN */
unsigned dcc_independent_64B:1;
bool scanout;
} gfx9;
} u;

14
src/gallium/drivers/radeonsi/si_texture.c
View file

@ -374,10 +374,8 @@ static void si_get_display_metadata(struct si_screen *sscreen,
else
*array_mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
*is_scanout = metadata->u.gfx9.swizzle_mode == 0 ||
metadata->u.gfx9.swizzle_mode % 4 == 2;
surf->u.gfx9.surf.swizzle_mode = metadata->u.gfx9.swizzle_mode;
*is_scanout = metadata->u.gfx9.scanout;
if (metadata->u.gfx9.dcc_offset_256B) {
surf->u.gfx9.display_dcc_pitch_max = metadata->u.gfx9.dcc_pitch_max;
@ -658,6 +656,7 @@ static void si_set_tex_bo_metadata(struct si_screen *sscreen,
if (sscreen->info.chip_class >= GFX9) {
md.u.gfx9.swizzle_mode = surface->u.gfx9.surf.swizzle_mode;
md.u.gfx9.scanout = (surface->flags & RADEON_SURF_SCANOUT) != 0;
if (tex->surface.dcc_offset && !tex->dcc_separate_buffer) {
uint64_t dcc_offset =
@ -808,12 +807,7 @@ static bool si_read_tex_bo_metadata(struct si_screen *sscreen,
if (sscreen->info.chip_class >= GFX8 &&
G_008F28_COMPRESSION_EN(desc[6])) {
/* Read DCC information.
*
* Some state trackers don't set the SCANOUT flag when
* importing displayable images, which affects PIPE_ALIGNED
* and RB_ALIGNED, so we need to recover them here.
*/
/* Read DCC information. */
switch (sscreen->info.chip_class) {
case GFX8:
tex->surface.dcc_offset = (uint64_t)desc[7] << 8;
@ -831,7 +825,7 @@ static bool si_read_tex_bo_metadata(struct si_screen *sscreen,
/* If DCC is unaligned, this can only be a displayable image. */
if (!tex->surface.u.gfx9.dcc.pipe_aligned &&
!tex->surface.u.gfx9.dcc.rb_aligned)
tex->surface.is_displayable = true;
assert(tex->surface.is_displayable);
break;
case GFX10:

5
src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
View file

@ -1204,6 +1204,9 @@ static unsigned eg_tile_split_rev(unsigned eg_tile_split)
}
}
#define AMDGPU_TILING_SCANOUT_SHIFT 63
#define AMDGPU_TILING_SCANOUT_MASK 0x1
static void amdgpu_buffer_get_metadata(struct pb_buffer *_buf,
struct radeon_bo_metadata *md)
{
@ -1226,6 +1229,7 @@ static void amdgpu_buffer_get_metadata(struct pb_buffer *_buf,
md->u.gfx9.dcc_offset_256B = AMDGPU_TILING_GET(tiling_flags, DCC_OFFSET_256B);
md->u.gfx9.dcc_pitch_max = AMDGPU_TILING_GET(tiling_flags, DCC_PITCH_MAX);
md->u.gfx9.dcc_independent_64B = AMDGPU_TILING_GET(tiling_flags, DCC_INDEPENDENT_64B);
md->u.gfx9.scanout = AMDGPU_TILING_GET(tiling_flags, SCANOUT);
} else {
md->u.legacy.microtile = RADEON_LAYOUT_LINEAR;
md->u.legacy.macrotile = RADEON_LAYOUT_LINEAR;
@ -1263,6 +1267,7 @@ static void amdgpu_buffer_set_metadata(struct pb_buffer *_buf,
tiling_flags |= AMDGPU_TILING_SET(DCC_OFFSET_256B, md->u.gfx9.dcc_offset_256B);
tiling_flags |= AMDGPU_TILING_SET(DCC_PITCH_MAX, md->u.gfx9.dcc_pitch_max);
tiling_flags |= AMDGPU_TILING_SET(DCC_INDEPENDENT_64B, md->u.gfx9.dcc_independent_64B);
tiling_flags |= AMDGPU_TILING_SET(SCANOUT, md->u.gfx9.scanout);
} else {
if (md->u.legacy.macrotile == RADEON_LAYOUT_TILED)
tiling_flags |= AMDGPU_TILING_SET(ARRAY_MODE, 4); /* 2D_TILED_THIN1 */